{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/129977"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/129977","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Accurately modeling the compute capabilities of computational storage devices","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","abstract_has_math":false,"creators":["Shah, Vijay R."],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Ghose, Saugata"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-07-23","date_published":"2025-07-23","updated_at":"2026-07-22T22:25:06Z","subjects":["Computational Storage Devices"],"languages":["en","eng"],"rights":["Copyright 2025, Vijay Shah"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/129977","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Ghose, Saugata"]},{"key":"dc:creator","label":"Author","values":["Shah, Vijay R."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-07-23","2025-08"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computational Storage Devices"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025, Vijay Shah"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/129977"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","The student, Vijay Shah, accepted the attached license on 2025-07-22 at 16:23.","The student, Vijay Shah, submitted this Thesis for approval on 2025-07-22 at 16:28.","This Thesis was approved for publication on 2025-07-23 at 09:27.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22699 on 2025-10-20 at 20:15:40","Many recent research efforts and prototypes for computational solid-state drives (SSDs) have leveraged additional logic, such as FPGAs or specialized accelerators, to offload computation from the host CPU and improve performance. However, these solutions often come with high cost and development overheads, limiting their scalability and feasibility in commercial deployments. In this work, we investigate whether existing resources already present in many modern SSDs, namely their built-in embedded multicore CPUs, can be used to support computational storage workloads without requiring expensive hardware additions. To facilitate this, we develop a full-system simulation framework based on SimpleSSD 2.0 that accurately models these embedded processors within both consumer and enterprise SSDs, including their interaction with firmware tasks and flash translation layers. Our simulator enables fine-grained control over core allocation, memory usage, and execution timing, making it possible to analyze the trade-offs involved in running user-defined computations directly on the SSD. We also provide a structured approach to our simulator design and reusable utility functions. This is designed to lower the barrier to entry for computational storage research and offer a high-fidelity environment for studying its potential benefits. Beyond building the simulator, we focus on evaluating whether the embedded cores in SSDs are powerful enough to handle general-purpose computation alongside their native responsibilities. This includes assessing performance, latency, and resource contention when multiple workloads are run concurrently. While standardization of computational storage remains an open challenge, we believe that exploring the viability of utilizing existing embedded CPUs is a crucial step toward more accessible and cost-effective solutions. Even when passing multiple requests to the SSD at once, we see that for a more advanced firmware configuration on an 8 core internal CPU, 57.08 percent of cycles are spent waiting on mutex locks and 4.78 percent are spent waiting on DRAM stalls. This suggests that there are many cycles available for computational storage, especially at higher core counts."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Accurately modeling the compute capabilities of computational storage devices"]}]}],"canonical_facts":{"dc:contributor":["Ghose, Saugata"],"dc:creator":["Shah, Vijay R."],"dc:date":["2025-07-23","2025-08"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","The student, Vijay Shah, accepted the attached license on 2025-07-22 at 16:23.","The student, Vijay Shah, submitted this Thesis for approval on 2025-07-22 at 16:28.","This Thesis was approved for publication on 2025-07-23 at 09:27.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22699 on 2025-10-20 at 20:15:40","Many recent research efforts and prototypes for computational solid-state drives (SSDs) have leveraged additional logic, such as FPGAs or specialized accelerators, to offload computation from the host CPU and improve performance. However, these solutions often come with high cost and development overheads, limiting their scalability and feasibility in commercial deployments. In this work, we investigate whether existing resources already present in many modern SSDs, namely their built-in embedded multicore CPUs, can be used to support computational storage workloads without requiring expensive hardware additions. To facilitate this, we develop a full-system simulation framework based on SimpleSSD 2.0 that accurately models these embedded processors within both consumer and enterprise SSDs, including their interaction with firmware tasks and flash translation layers. Our simulator enables fine-grained control over core allocation, memory usage, and execution timing, making it possible to analyze the trade-offs involved in running user-defined computations directly on the SSD. We also provide a structured approach to our simulator design and reusable utility functions. This is designed to lower the barrier to entry for computational storage research and offer a high-fidelity environment for studying its potential benefits. Beyond building the simulator, we focus on evaluating whether the embedded cores in SSDs are powerful enough to handle general-purpose computation alongside their native responsibilities. This includes assessing performance, latency, and resource contention when multiple workloads are run concurrently. While standardization of computational storage remains an open challenge, we believe that exploring the viability of utilizing existing embedded CPUs is a crucial step toward more accessible and cost-effective solutions. Even when passing multiple requests to the SSD at once, we see that for a more advanced firmware configuration on an 8 core internal CPU, 57.08 percent of cycles are spent waiting on mutex locks and 4.78 percent are spent waiting on DRAM stalls. This suggests that there are many cycles available for computational storage, especially at higher core counts."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/129977"],"dc:language":["en","eng"],"dc:rights":["Copyright 2025, Vijay Shah"],"dc:subject":["Computational Storage Devices"],"dc:title":["Accurately modeling the compute capabilities of computational storage devices"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:06Z"}