{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/129936"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/129936","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Enhancing system-level efficiency using SNICs","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","abstract_has_math":false,"creators":["Vanavasam, Srikar"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Kim, Nam Sung"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-07-13","date_published":"2025-07-13","updated_at":"2026-07-22T22:25:06Z","subjects":["Computer Architecture","Network","Datacenter"],"languages":["en","eng"],"rights":["Copyright 2025 Srikar Vanavasam"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/129936","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kim, Nam Sung"]},{"key":"dc:creator","label":"Author","values":["Vanavasam, Srikar"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-07-13","2025-08"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Architecture","Network","Datacenter"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Srikar Vanavasam"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/129936"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","The student, Srikar Vanavasam, accepted the attached license on 2025-07-11 at 16:31.","The student, Srikar Vanavasam, submitted this Thesis for approval on 2025-07-11 at 16:37.","This Thesis was approved for publication on 2025-07-13 at 11:50.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22527 on 2025-10-20 at 20:15:12","The rapid increase in network bandwidth continues to outpace the scaling of single-thread CPU performance, creating a significant \"datacenter tax\" where host CPUs are consumed by infrastructure tasks. To address this, modern servers employ a variety of specialized hardware, including on-chip accelerators and programmable Smart Network Interface Cards (SNICs). This thesis provides a multi-faceted architectural analysis of these components, focusing on performance trade-offs, next-generation interconnects, and novel offload frameworks. First, a characterization of a modern host CPU (Intel Sapphire Rapids) versus an integrated SNIC processor (NVIDIA BlueField-3) reveals the fundamental performance and energy trade-offs of executing network functions, establishing that the optimal processing location is heavily dependent on workload intensity. Second, the host interconnect is addressed by characterizing the performance of offloading kernel subsystems (\\texttt{zswap} and \\texttt{ksm}) over the new Compute Express Link (CXL) protocol versus traditional PCIe. The results quantify the latency advantages of CXL for fine-grained, latency-sensitive host-accelerator communication. Third, a novel framework, AccDirect, is presented. It leverages an SNIC to orchestrate PCIe Peer-to-Peer (P2P) communication with an on-chip accelerator, the Intel Dynamic Load Balancer (DLB). An end-to-end comparison demonstrates that this approach significantly reduces system power and improves application throughput compared to traditional software-based load balancers by eliminating the host CPU from the data path. Finally, a deep-dive characterization of a novel programmable engine on a state-of-the-art SNIC, the NVIDIA BlueField-3 Data Path Accelerator (DPA), reveals its architectural properties and performance bottlenecks, highlighting the profound impact of its memory subsystem on overall performance. Collectively, these studies provide critical insights for architects and practitioners seeking to build and optimize efficient, next-generation data center systems."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Enhancing system-level efficiency using SNICs"]}]}],"canonical_facts":{"dc:contributor":["Kim, Nam Sung"],"dc:creator":["Vanavasam, Srikar"],"dc:date":["2025-07-13","2025-08"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","The student, Srikar Vanavasam, accepted the attached license on 2025-07-11 at 16:31.","The student, Srikar Vanavasam, submitted this Thesis for approval on 2025-07-11 at 16:37.","This Thesis was approved for publication on 2025-07-13 at 11:50.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22527 on 2025-10-20 at 20:15:12","The rapid increase in network bandwidth continues to outpace the scaling of single-thread CPU performance, creating a significant \"datacenter tax\" where host CPUs are consumed by infrastructure tasks. To address this, modern servers employ a variety of specialized hardware, including on-chip accelerators and programmable Smart Network Interface Cards (SNICs). This thesis provides a multi-faceted architectural analysis of these components, focusing on performance trade-offs, next-generation interconnects, and novel offload frameworks. First, a characterization of a modern host CPU (Intel Sapphire Rapids) versus an integrated SNIC processor (NVIDIA BlueField-3) reveals the fundamental performance and energy trade-offs of executing network functions, establishing that the optimal processing location is heavily dependent on workload intensity. Second, the host interconnect is addressed by characterizing the performance of offloading kernel subsystems (\\texttt{zswap} and \\texttt{ksm}) over the new Compute Express Link (CXL) protocol versus traditional PCIe. The results quantify the latency advantages of CXL for fine-grained, latency-sensitive host-accelerator communication. Third, a novel framework, AccDirect, is presented. It leverages an SNIC to orchestrate PCIe Peer-to-Peer (P2P) communication with an on-chip accelerator, the Intel Dynamic Load Balancer (DLB). An end-to-end comparison demonstrates that this approach significantly reduces system power and improves application throughput compared to traditional software-based load balancers by eliminating the host CPU from the data path. Finally, a deep-dive characterization of a novel programmable engine on a state-of-the-art SNIC, the NVIDIA BlueField-3 Data Path Accelerator (DPA), reveals its architectural properties and performance bottlenecks, highlighting the profound impact of its memory subsystem on overall performance. Collectively, these studies provide critical insights for architects and practitioners seeking to build and optimize efficient, next-generation data center systems."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/129936"],"dc:language":["en","eng"],"dc:rights":["Copyright 2025 Srikar Vanavasam"],"dc:subject":["Computer Architecture","Network","Datacenter"],"dc:title":["Enhancing system-level efficiency using SNICs"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:06Z"}