{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/129929"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/129929","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Supporting write-through caching with high-performance TSO for resilient CXL systems","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","abstract_has_math":false,"creators":["Ocalan, Burak"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Torrellas, Josep"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-07-11","date_published":"2025-07-11","updated_at":"2026-07-22T22:25:06Z","subjects":["Write-through","Tso","Cxl"],"languages":["en","eng"],"rights":["Copyright 2025 Burak Ocalan"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/129929","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Torrellas, Josep"]},{"key":"dc:creator","label":"Author","values":["Ocalan, Burak"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-07-11","2025-08"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Write-through","Tso","Cxl"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Burak Ocalan"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/129929"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","The student, Burak Ocalan, accepted the attached license on 2025-07-10 at 09:47.","The student, Burak Ocalan, submitted this Thesis for approval on 2025-07-10 at 11:59.","This Thesis was approved for publication on 2025-07-11 at 14:06.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22481 on 2025-10-20 at 20:15:08","Current multiprocessors that support the total store order (TSO) memory consistency model invariably use write-back (WB) caches. When their hardware needs to issue write-through (WT) stores as in uncached operations, they deliver dismal performance: writes to memory have to be fully serialized, often forcing the program to observe the full latency of a round-trip to memory. To solve this problem, this thesis presents a novel architecture that supports high-performance TSO for WT caching environments. The architecture, called PhasedStore, involves extending the store queue of the core with additional states. Individual WT stores operate in two phases, which allow them to fully overlap with other stores and still satisfy TSO. PhasedStore is useful in environments that require a WT cache coherence protocol. This is the case in a setting that this thesis explores: a cache-coherent CXL distributed shared memory system in the presence of compute node failures. In this environment, to simplify recovery, we support a WT directory-based protocol which guarantees that stores are propagated to the CXL memory before updating the caches. Our evaluation shows that PhasedStore is very effective. Compared to a conventional approach to enforce TSO in a WT protocol, PhasedStore reduces the average execution time of a set of parallel applications by 2.21x. Further, the applications' execution time is only 1.40x higher than with a TSO WB protocol that includes no resilience consideration."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Supporting write-through caching with high-performance TSO for resilient CXL systems"]}]}],"canonical_facts":{"dc:contributor":["Torrellas, Josep"],"dc:creator":["Ocalan, Burak"],"dc:date":["2025-07-11","2025-08"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-20 without embargo terms","The student, Burak Ocalan, accepted the attached license on 2025-07-10 at 09:47.","The student, Burak Ocalan, submitted this Thesis for approval on 2025-07-10 at 11:59.","This Thesis was approved for publication on 2025-07-11 at 14:06.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22481 on 2025-10-20 at 20:15:08","Current multiprocessors that support the total store order (TSO) memory consistency model invariably use write-back (WB) caches. When their hardware needs to issue write-through (WT) stores as in uncached operations, they deliver dismal performance: writes to memory have to be fully serialized, often forcing the program to observe the full latency of a round-trip to memory. To solve this problem, this thesis presents a novel architecture that supports high-performance TSO for WT caching environments. The architecture, called PhasedStore, involves extending the store queue of the core with additional states. Individual WT stores operate in two phases, which allow them to fully overlap with other stores and still satisfy TSO. PhasedStore is useful in environments that require a WT cache coherence protocol. This is the case in a setting that this thesis explores: a cache-coherent CXL distributed shared memory system in the presence of compute node failures. In this environment, to simplify recovery, we support a WT directory-based protocol which guarantees that stores are propagated to the CXL memory before updating the caches. Our evaluation shows that PhasedStore is very effective. Compared to a conventional approach to enforce TSO in a WT protocol, PhasedStore reduces the average execution time of a set of parallel applications by 2.21x. Further, the applications' execution time is only 1.40x higher than with a TSO WB protocol that includes no resilience consideration."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/129929"],"dc:language":["en","eng"],"dc:rights":["Copyright 2025 Burak Ocalan"],"dc:subject":["Write-through","Tso","Cxl"],"dc:title":["Supporting write-through caching with high-performance TSO for resilient CXL systems"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:06Z"}