{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/129319"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/129319","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Signal integrity diagnosis and distributed physical-based transmission line model development for PCIe 5.0 connector","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms","abstract_has_math":false,"creators":["He, Yulin"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Feng, Milton"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-05-09","date_published":"2025-05-09","updated_at":"2026-07-22T22:25:04Z","subjects":["Signal Integrity","Tranmission Line","Equivalent Circuit","5g","High Speed","Pcie","Physical-based Model","Failure Diagnosis"],"languages":["en","eng"],"rights":["Copyright 2025 Yulin He"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/129319","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Feng, Milton"]},{"key":"dc:creator","label":"Author","values":["He, Yulin"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-05-09","2025-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Signal Integrity","Tranmission Line","Equivalent Circuit","5g","High Speed","Pcie","Physical-based Model","Failure Diagnosis"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Yulin He"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/129319"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms","The student, Yulin He, accepted the attached license on 2025-05-04 at 15:21.","The student, Yulin He, submitted this Thesis for approval on 2025-05-04 at 15:33.","This Thesis was approved for publication on 2025-05-09 at 15:37.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22203 on 2025-10-19 at 18:12:32","High-speed connector design demands a delicate balance between simulation accuracy and rapid signal-integrity (SI) diagnosis. This thesis introduces a novel design tool based on a distributed physical-based transmission-line (dPBTL) model to overcome the limitations of traditional FEM simulations. By transforming complex 3-D PCIe 5.0 connector structures into cascaded 1-D transmission-line segments, the proposed method enables fast, accurate predictions of electrical performance up to 60 GHz while revealing localized effects such as impedance discontinuities, resonances, and loss mechanisms. Moreover, by segmenting the connector into intrinsic and extrinsic subsections—with and without add-in-card (AIC) or baseboard mating— the approach facilitates targeted SI analysis and time-efficient design modifications. This methodology not only significantly reduces simulation time and computational resources but also provides a robust framework for real-time design pathfinding and optimization in high-speed interconnects."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Signal integrity diagnosis and distributed physical-based transmission line model development for PCIe 5.0 connector"]}]}],"canonical_facts":{"dc:contributor":["Feng, Milton"],"dc:creator":["He, Yulin"],"dc:date":["2025-05-09","2025-05"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms","The student, Yulin He, accepted the attached license on 2025-05-04 at 15:21.","The student, Yulin He, submitted this Thesis for approval on 2025-05-04 at 15:33.","This Thesis was approved for publication on 2025-05-09 at 15:37.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22203 on 2025-10-19 at 18:12:32","High-speed connector design demands a delicate balance between simulation accuracy and rapid signal-integrity (SI) diagnosis. This thesis introduces a novel design tool based on a distributed physical-based transmission-line (dPBTL) model to overcome the limitations of traditional FEM simulations. By transforming complex 3-D PCIe 5.0 connector structures into cascaded 1-D transmission-line segments, the proposed method enables fast, accurate predictions of electrical performance up to 60 GHz while revealing localized effects such as impedance discontinuities, resonances, and loss mechanisms. Moreover, by segmenting the connector into intrinsic and extrinsic subsections—with and without add-in-card (AIC) or baseboard mating— the approach facilitates targeted SI analysis and time-efficient design modifications. This methodology not only significantly reduces simulation time and computational resources but also provides a robust framework for real-time design pathfinding and optimization in high-speed interconnects."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/129319"],"dc:language":["en","eng"],"dc:rights":["Copyright 2025 Yulin He"],"dc:subject":["Signal Integrity","Tranmission Line","Equivalent Circuit","5g","High Speed","Pcie","Physical-based Model","Failure Diagnosis"],"dc:title":["Signal integrity diagnosis and distributed physical-based transmission line model development for PCIe 5.0 connector"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:04Z"}