{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/129308"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/129308","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms","abstract_has_math":false,"creators":["Yuan, Chentai"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Wang, Dong Kai"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-05-08","date_published":"2025-05-08","updated_at":"2026-07-22T22:25:04Z","subjects":["Risc-v Architecture","Microarchitecture Optimization","Graph-based Hardware Modeling"],"languages":["en","eng"],"rights":["Chentai Yuan"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/129308","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Wang, Dong Kai"]},{"key":"dc:creator","label":"Author","values":["Yuan, Chentai"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-05-08","2025-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Risc-v Architecture","Microarchitecture Optimization","Graph-based Hardware Modeling"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Chentai Yuan"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/129308"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms","The student, Chentai Yuan, accepted the attached license on 2025-05-02 at 10:05.","The student, Chentai Yuan, submitted this Thesis for approval on 2025-05-02 at 10:24.","This Thesis was approved for publication on 2025-05-08 at 15:24.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22174 on 2025-10-19 at 18:11:34","As the demand for computing power continues to grow in the modern world, the chip industry has been driven to develop increasingly advanced processors to meet these growing needs. The microarchitecture of modern processors has become very complex, making it more challenging to achieve sustained improvements in performance and efficiency with each new generation. We explore two novel approaches to optimize the efficiency of modern processors: ArchGen, a design-space exploration framework that models processor microarchitecture using graphs, and MESA, a dataflow mapper that performs dynamic binary translation for reconfigurable accelerators. ArchGen introduces a graph representation of hardware architecture to allow rapid design estimations and iterative optimization. MESA, on the other hand, introduces an on-chip hardware controller that monitors running programs on the CPU and offloads them to an accelerator when suitable. This thesis delivers two major contributions: the development of a composable RISC-V vector processor as a base RTL library for ArchGen and the verification of an AXI4 port within MESA. We demonstrate that ArchGen can use our custom RISC-V processor as a baseline for iterative optimization and hardware synthesis. The addition of an AXI4-compliant port to MESA allows it to easily interface with other devices in a system-on-chip. Both methods are evaluated to test their effectiveness and correctness through hardware simulation, synthesis, and performance modeling."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware"]}]}],"canonical_facts":{"dc:contributor":["Wang, Dong Kai"],"dc:creator":["Yuan, Chentai"],"dc:date":["2025-05-08","2025-05"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms","The student, Chentai Yuan, accepted the attached license on 2025-05-02 at 10:05.","The student, Chentai Yuan, submitted this Thesis for approval on 2025-05-02 at 10:24.","This Thesis was approved for publication on 2025-05-08 at 15:24.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22174 on 2025-10-19 at 18:11:34","As the demand for computing power continues to grow in the modern world, the chip industry has been driven to develop increasingly advanced processors to meet these growing needs. The microarchitecture of modern processors has become very complex, making it more challenging to achieve sustained improvements in performance and efficiency with each new generation. We explore two novel approaches to optimize the efficiency of modern processors: ArchGen, a design-space exploration framework that models processor microarchitecture using graphs, and MESA, a dataflow mapper that performs dynamic binary translation for reconfigurable accelerators. ArchGen introduces a graph representation of hardware architecture to allow rapid design estimations and iterative optimization. MESA, on the other hand, introduces an on-chip hardware controller that monitors running programs on the CPU and offloads them to an accelerator when suitable. This thesis delivers two major contributions: the development of a composable RISC-V vector processor as a base RTL library for ArchGen and the verification of an AXI4 port within MESA. We demonstrate that ArchGen can use our custom RISC-V processor as a baseline for iterative optimization and hardware synthesis. The addition of an AXI4-compliant port to MESA allows it to easily interface with other devices in a system-on-chip. Both methods are evaluated to test their effectiveness and correctness through hardware simulation, synthesis, and performance modeling."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/129308"],"dc:language":["en","eng"],"dc:rights":["Chentai Yuan"],"dc:subject":["Risc-v Architecture","Microarchitecture Optimization","Graph-based Hardware Modeling"],"dc:title":["Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:04Z"}