{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/124609"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/124609","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"EMACS: efficient CXL-based memory access counters","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","abstract_has_math":false,"creators":["Yu, Zeduo (Douglas)"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kim, Nam Sung"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2024,"date_issued":"2024-05","date_published":"2024-05","updated_at":"2026-07-22T22:25:02Z","subjects":["Cxl Memory","Computer Architecture","Memory Subsystem"],"languages":["en","eng"],"rights":["Copyright 2024 Zeduo (Douglas) Yu"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/124609","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kim, Nam Sung"]},{"key":"dc:creator","label":"Author","values":["Yu, Zeduo (Douglas)"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2024-05","2024-05-02"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Cxl Memory","Computer Architecture","Memory Subsystem"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2024 Zeduo (Douglas) Yu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/124609"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","The student, Zedou (Douglas) Yu, accepted the attached license on 2024-05-02 at 11:15.","The student, Zedou (Douglas) Yu, submitted this Thesis for approval on 2024-05-02 at 11:24.","This Thesis was approved for publication on 2024-05-02 at 16:05.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20757 on 2024-09-16 at 00:45:04","This paper presents an efficient solution, EMACS, to count memory accesses for applications utilizing the CXL memory on an FPGA platform. CXL is a promising alternative to the mainstream DDR memory interface that can expand the capacity and bandwidth of a memory system. One type of CXL memory device comes in the form factor of an FPGA with a hard IP, providing extra programmability for its user and thus allowing the implementation of EMACS. EMACS consists of the following 3 key components. 1) A customized hardware logic on the FPGA that fulfills the counting mechanism. 2) A compatible kernel module to handle the communication to the logic. 3) A shell script that automates the control sequence to readily profile the memory accesses for any application. The mechanism and implementation of all three components will be elaborated in this paper, as well as the challenges met in the implementation process. In the end, the outcome of the EMACS tests on several benchmarks will be shown in the form of heatmap graphs."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["EMACS: efficient CXL-based memory access counters"]}]}],"canonical_facts":{"dc:contributor":["Kim, Nam Sung"],"dc:creator":["Yu, Zeduo (Douglas)"],"dc:date":["2024-05","2024-05-02"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","The student, Zedou (Douglas) Yu, accepted the attached license on 2024-05-02 at 11:15.","The student, Zedou (Douglas) Yu, submitted this Thesis for approval on 2024-05-02 at 11:24.","This Thesis was approved for publication on 2024-05-02 at 16:05.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20757 on 2024-09-16 at 00:45:04","This paper presents an efficient solution, EMACS, to count memory accesses for applications utilizing the CXL memory on an FPGA platform. CXL is a promising alternative to the mainstream DDR memory interface that can expand the capacity and bandwidth of a memory system. One type of CXL memory device comes in the form factor of an FPGA with a hard IP, providing extra programmability for its user and thus allowing the implementation of EMACS. EMACS consists of the following 3 key components. 1) A customized hardware logic on the FPGA that fulfills the counting mechanism. 2) A compatible kernel module to handle the communication to the logic. 3) A shell script that automates the control sequence to readily profile the memory accesses for any application. The mechanism and implementation of all three components will be elaborated in this paper, as well as the challenges met in the implementation process. In the end, the outcome of the EMACS tests on several benchmarks will be shown in the form of heatmap graphs."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/124609"],"dc:language":["en","eng"],"dc:rights":["Copyright 2024 Zeduo (Douglas) Yu"],"dc:subject":["Cxl Memory","Computer Architecture","Memory Subsystem"],"dc:title":["EMACS: efficient CXL-based memory access counters"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:02Z"}