{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/124588"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/124588","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Towards real-time high-resolution edge detection: A highly efficient FPGA implementation of the Canny algorithm","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","abstract_has_math":false,"creators":["Zhang, Zhengyang"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kindratenko, Volodymyr"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2024,"date_issued":"2024-05","date_published":"2024-05","updated_at":"2026-07-22T22:25:02Z","subjects":["Fpga Implementation","Canny Edge Detection Algorithm","High-level Synthesis (hls)"],"languages":["en","eng"],"rights":["Copyright 2024 Zhengyang Zhang"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/124588","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kindratenko, Volodymyr"]},{"key":"dc:creator","label":"Author","values":["Zhang, Zhengyang"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2024-05","2024-04-30"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Fpga Implementation","Canny Edge Detection Algorithm","High-level Synthesis (hls)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2024 Zhengyang Zhang"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/124588"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","The student, Zhengyang Zhang, accepted the attached license on 2024-04-26 at 14:03.","The student, Zhengyang Zhang, submitted this Thesis for approval on 2024-04-26 at 14:23.","This Thesis was approved for publication on 2024-04-30 at 09:25.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20664 on 2024-09-16 at 00:44:48","With the rapid development of computer vision technology in recent years, image edge detection has been playing an increasingly important role in fields such as object recognition, image segmentation, and image enhancement. The Canny edge detection algorithm stands out among various edge detection algorithms for its accuracy and robustness. However, its high computational complexity makes it challenging to meet the requirements of real-time processing. This work presents an optimized FPGA-based design for Canny edge detection that significantly enhances execution efficiency by leveraging High-level Synthesis (HLS) to achieve pipelined computation and communication. The main contributions of this work are as follows: (1) proposing a streaming-based data movement strategy combined with a multi-sliding window architecture, significantly enhancing data throughput and computational efficiency; (3) constructing fully pipelined compute units to achieve high-throughput edge detection processing; (4) deploying our design on the OpenCL framework and testing its performance on actual hardware, further enhancing the acceleration effect through OpenCL's out-of-order execution feature. After optimization, the proposed design achieves an execution latency of 61 microseconds for edge detection on 512×512 resolution images when operating at 300MHz, with a simulation latency of 32.8 microseconds at the same frequency, representing a 3.67-fold improvement over the fastest open-source FPGA implementation and meeting the requirements for real-time processing."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Towards real-time high-resolution edge detection: A highly efficient FPGA implementation of the Canny algorithm"]}]}],"canonical_facts":{"dc:contributor":["Kindratenko, Volodymyr"],"dc:creator":["Zhang, Zhengyang"],"dc:date":["2024-05","2024-04-30"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","The student, Zhengyang Zhang, accepted the attached license on 2024-04-26 at 14:03.","The student, Zhengyang Zhang, submitted this Thesis for approval on 2024-04-26 at 14:23.","This Thesis was approved for publication on 2024-04-30 at 09:25.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20664 on 2024-09-16 at 00:44:48","With the rapid development of computer vision technology in recent years, image edge detection has been playing an increasingly important role in fields such as object recognition, image segmentation, and image enhancement. The Canny edge detection algorithm stands out among various edge detection algorithms for its accuracy and robustness. However, its high computational complexity makes it challenging to meet the requirements of real-time processing. This work presents an optimized FPGA-based design for Canny edge detection that significantly enhances execution efficiency by leveraging High-level Synthesis (HLS) to achieve pipelined computation and communication. The main contributions of this work are as follows: (1) proposing a streaming-based data movement strategy combined with a multi-sliding window architecture, significantly enhancing data throughput and computational efficiency; (3) constructing fully pipelined compute units to achieve high-throughput edge detection processing; (4) deploying our design on the OpenCL framework and testing its performance on actual hardware, further enhancing the acceleration effect through OpenCL's out-of-order execution feature. After optimization, the proposed design achieves an execution latency of 61 microseconds for edge detection on 512×512 resolution images when operating at 300MHz, with a simulation latency of 32.8 microseconds at the same frequency, representing a 3.67-fold improvement over the fastest open-source FPGA implementation and meeting the requirements for real-time processing."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/124588"],"dc:language":["en","eng"],"dc:rights":["Copyright 2024 Zhengyang Zhang"],"dc:subject":["Fpga Implementation","Canny Edge Detection Algorithm","High-level Synthesis (hls)"],"dc:title":["Towards real-time high-resolution edge detection: A highly efficient FPGA implementation of the Canny algorithm"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:02Z"}