{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/122175"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/122175","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Optimizing network data movement in server class microprocessors","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-12-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-12-01","abstract_has_math":false,"creators":["Agarwal, Siddharth"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kim, Nam Sung"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2023,"date_issued":"2023-12","date_published":"2023-12","updated_at":"2026-07-22T22:25:00Z","subjects":["Networking","Computer Architechutre"],"languages":["en","eng"],"rights":["Copyright 2023 Siddharth Agarwal"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/122175","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kim, Nam Sung"]},{"key":"dc:creator","label":"Author","values":["Agarwal, Siddharth"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2023-12","2023-12-06"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Networking","Computer Architechutre"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2023 Siddharth Agarwal"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/122175"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-12-01","The student, Siddharth Agarwal, accepted the attached license on 2023-12-05 at 14:27.","The student, Siddharth Agarwal, submitted this Thesis for approval on 2023-12-05 at 14:36.","This Thesis was approved for publication on 2023-12-06 at 11:02.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20145 on 2024-03-01 at 13:32:40","High-bandwidth network interface cards (NICs), each capable of transferring 100s of Gigabits per second, are making inroads into the servers of next generation data centers. Such unprecedented data delivery rates impose immense pressure, especially on the server’s memory subsystem, as NICs first transfer network data to DRAM before processing. The cache hierarchy has evolved in response, supporting a direct data input-output (DDIO) technology to place network data directly in the last-level cache (LLC). Subsequently, various policies have been explored to manage such LLCs and have proven effective in reducing service latency and memory bandwidth consumption of network applications. However, the more recent evolution of the cache hierarchy decreased the size of LLC per core but significantly increased that of mid-level cache (MLC) with a non-inclusive policy. This calls for a re-examination of the DDIO as mentioned above technology and management policies. In this work, we first develop a framework for modeling 100 Gigabit networking in a cycle-accurate architectural simulator. We also identify shortcomings of the static data placement policy, placing network data to LLC first, and the non-inclusive policy with a commercial server system. We then propose an intelligent direct input-output (IDIO) technology that extends DDIO to MLC and provides three synergistic mechanisms: (1) self- invalidating I/O buffer, (2) network-driven MLC prefetching, and (3) selective direct DRAM access. Our detailed experiments using a full-system simulator show that IDIO significantly reduces data movement (up to 84% MLC and LLC write-back reduction), provides LLC isolation (up to 22% performance improvement), and improves tail latency (up to 38% reduction in 99 percentile latency) for receive-intensive network applications."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Optimizing network data movement in server class microprocessors"]}]}],"canonical_facts":{"dc:contributor":["Kim, Nam Sung"],"dc:creator":["Agarwal, Siddharth"],"dc:date":["2023-12","2023-12-06"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-12-01","The student, Siddharth Agarwal, accepted the attached license on 2023-12-05 at 14:27.","The student, Siddharth Agarwal, submitted this Thesis for approval on 2023-12-05 at 14:36.","This Thesis was approved for publication on 2023-12-06 at 11:02.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20145 on 2024-03-01 at 13:32:40","High-bandwidth network interface cards (NICs), each capable of transferring 100s of Gigabits per second, are making inroads into the servers of next generation data centers. Such unprecedented data delivery rates impose immense pressure, especially on the server’s memory subsystem, as NICs first transfer network data to DRAM before processing. The cache hierarchy has evolved in response, supporting a direct data input-output (DDIO) technology to place network data directly in the last-level cache (LLC). Subsequently, various policies have been explored to manage such LLCs and have proven effective in reducing service latency and memory bandwidth consumption of network applications. However, the more recent evolution of the cache hierarchy decreased the size of LLC per core but significantly increased that of mid-level cache (MLC) with a non-inclusive policy. This calls for a re-examination of the DDIO as mentioned above technology and management policies. In this work, we first develop a framework for modeling 100 Gigabit networking in a cycle-accurate architectural simulator. We also identify shortcomings of the static data placement policy, placing network data to LLC first, and the non-inclusive policy with a commercial server system. We then propose an intelligent direct input-output (IDIO) technology that extends DDIO to MLC and provides three synergistic mechanisms: (1) self- invalidating I/O buffer, (2) network-driven MLC prefetching, and (3) selective direct DRAM access. Our detailed experiments using a full-system simulator show that IDIO significantly reduces data movement (up to 84% MLC and LLC write-back reduction), provides LLC isolation (up to 22% performance improvement), and improves tail latency (up to 38% reduction in 99 percentile latency) for receive-intensive network applications."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/122175"],"dc:language":["en","eng"],"dc:rights":["Copyright 2023 Siddharth Agarwal"],"dc:subject":["Networking","Computer Architechutre"],"dc:title":["Optimizing network data movement in server class microprocessors"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:00Z"}