{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/121440"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/121440","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Understanding interactions between chip architecture and uncertainties in semiconductor supply and demand","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-12-04 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-12-04 without embargo terms","abstract_has_math":false,"creators":["Kanungo, Ramakrishna"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kumar, Rakesh"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2023,"date_issued":"2023-08","date_published":"2023-08","updated_at":"2026-07-22T22:24:57Z","subjects":["Semiconductors","Supply Chain Resilience"],"languages":["en","eng"],"rights":["Copyright 2023 Ramakrishna Kanungo"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/121440","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kumar, Rakesh"]},{"key":"dc:creator","label":"Author","values":["Kanungo, Ramakrishna"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2023-08","2023-07-17"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Semiconductors","Supply Chain Resilience"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2023 Ramakrishna Kanungo"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/121440"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-12-04 without embargo terms","The student, Ramakrishna Kanungo, accepted the attached license on 2023-06-30 at 01:35.","The student, Ramakrishna Kanungo, submitted this Thesis for approval on 2023-06-30 at 01:43.","This Thesis was approved for publication on 2023-07-17 at 09:01.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19478 on 2023-12-04 at 17:00:17","Mitigating losses from supply and demand volatility in the semiconductor supply chain and market has traditionally been cast as a logistics and fore- casting problem. We investigate how the architecture of a family of chips influences how it is affected by supply and demand uncertainties. We observe that semiconductor supply chains become fragile, in part, due to single de- mand paths, where one chip can satisfy only one demand. Chip architects can enable multiple paths to satisfy a chip demand, which improves supply chain resilience. Based on this observation, we study composition and adaptation as architectural strategies to improve resilience to volatility and also intro- duce a third strategy of dispersion. These strategies allow multiple paths to satisfy a given chip demand. We develop a model to analyze the impact of these architectural techniques on supply chain costs under different regimes of uncertainties and evaluate what happens when they are combined. We present several interesting and even counter-intuitive observations about the product configurations and market conditions where these interventions are impactful and where they are not. In all, we show that product redesign sup- ported by architectural changes can mitigate nearly half of the losses caused by supply and demand volatility. As far as we know, this is the first such investigation concerning chip architecture."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Understanding interactions between chip architecture and uncertainties in semiconductor supply and demand"]}]}],"canonical_facts":{"dc:contributor":["Kumar, Rakesh"],"dc:creator":["Kanungo, Ramakrishna"],"dc:date":["2023-08","2023-07-17"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-12-04 without embargo terms","The student, Ramakrishna Kanungo, accepted the attached license on 2023-06-30 at 01:35.","The student, Ramakrishna Kanungo, submitted this Thesis for approval on 2023-06-30 at 01:43.","This Thesis was approved for publication on 2023-07-17 at 09:01.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19478 on 2023-12-04 at 17:00:17","Mitigating losses from supply and demand volatility in the semiconductor supply chain and market has traditionally been cast as a logistics and fore- casting problem. We investigate how the architecture of a family of chips influences how it is affected by supply and demand uncertainties. We observe that semiconductor supply chains become fragile, in part, due to single de- mand paths, where one chip can satisfy only one demand. Chip architects can enable multiple paths to satisfy a chip demand, which improves supply chain resilience. Based on this observation, we study composition and adaptation as architectural strategies to improve resilience to volatility and also intro- duce a third strategy of dispersion. These strategies allow multiple paths to satisfy a given chip demand. We develop a model to analyze the impact of these architectural techniques on supply chain costs under different regimes of uncertainties and evaluate what happens when they are combined. We present several interesting and even counter-intuitive observations about the product configurations and market conditions where these interventions are impactful and where they are not. In all, we show that product redesign sup- ported by architectural changes can mitigate nearly half of the losses caused by supply and demand volatility. As far as we know, this is the first such investigation concerning chip architecture."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/121440"],"dc:language":["en","eng"],"dc:rights":["Copyright 2023 Ramakrishna Kanungo"],"dc:subject":["Semiconductors","Supply Chain Resilience"],"dc:title":["Understanding interactions between chip architecture and uncertainties in semiconductor supply and demand"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:57Z"}