{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/121353"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/121353","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Latency insertion method for fast high-speed link and IC simulation","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01","abstract_has_math":false,"creators":["Zhou, Yi"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Schutt-Ainé, José E."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2023,"date_issued":"2023-08","date_published":"2023-08","updated_at":"2026-07-22T22:24:57Z","subjects":["Latency Insertion Method","High-speed Link","Eye Diagram","Finfet","Bsim-cmg"],"languages":["en","eng"],"rights":["Copyright 2023 Yi Zhou"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/121353","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Schutt-Ainé, José E."]},{"key":"dc:creator","label":"Author","values":["Zhou, Yi"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2023-08","2023-07-20"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Latency Insertion Method","High-speed Link","Eye Diagram","Finfet","Bsim-cmg"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2023 Yi Zhou"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/121353"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01","The student, Yi Zhou, accepted the attached license on 2023-07-19 at 01:01.","The student, Yi Zhou, submitted this Thesis for approval on 2023-07-19 at 01:20.","This Thesis was approved for publication on 2023-07-20 at 08:49.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19618 on 2023-12-04 at 17:18:28","This thesis focuses on the Latency Insertion Method (LIM) for high-speed link and IC simulation. LIM is a transient simulation algorithm for circuits. Compared to Modified Nodal Analysis (MNA) methods such as SPICE, LIM exhibits linear computational complexity, which makes it faster than almost all the commercial software, especially for large-scale circuits. For high-speed link simulation, the LIM method for eye diagram simulation are first presented for both situations without and with crosstalk. The proposed method is compared to commercial software to prove that LIM can provide accurate and fast eye diagram simulations. For IC simulation, this thesis focuses on the latest technology that is 3-D FinFET. We presented LIM algorithms for both DC and transient FinFET simulation. By implementing the BSIM-CMG compact model, accurate and fast simulations can be achieved."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Latency insertion method for fast high-speed link and IC simulation"]}]}],"canonical_facts":{"dc:contributor":["Schutt-Ainé, José E."],"dc:creator":["Zhou, Yi"],"dc:date":["2023-08","2023-07-20"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01","The student, Yi Zhou, accepted the attached license on 2023-07-19 at 01:01.","The student, Yi Zhou, submitted this Thesis for approval on 2023-07-19 at 01:20.","This Thesis was approved for publication on 2023-07-20 at 08:49.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19618 on 2023-12-04 at 17:18:28","This thesis focuses on the Latency Insertion Method (LIM) for high-speed link and IC simulation. LIM is a transient simulation algorithm for circuits. Compared to Modified Nodal Analysis (MNA) methods such as SPICE, LIM exhibits linear computational complexity, which makes it faster than almost all the commercial software, especially for large-scale circuits. For high-speed link simulation, the LIM method for eye diagram simulation are first presented for both situations without and with crosstalk. The proposed method is compared to commercial software to prove that LIM can provide accurate and fast eye diagram simulations. For IC simulation, this thesis focuses on the latest technology that is 3-D FinFET. We presented LIM algorithms for both DC and transient FinFET simulation. By implementing the BSIM-CMG compact model, accurate and fast simulations can be achieved."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/121353"],"dc:language":["en","eng"],"dc:rights":["Copyright 2023 Yi Zhou"],"dc:subject":["Latency Insertion Method","High-speed Link","Eye Diagram","Finfet","Bsim-cmg"],"dc:title":["Latency insertion method for fast high-speed link and IC simulation"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:57Z"}