{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/121310"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/121310","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Analyzing and improving cache memory instruction","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01","abstract_has_math":false,"creators":["Mahmood, Muhammad Suleman"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Herman, Geoffrey","Zilles, Craig","Patel, Sanjay","Franklin, Diana"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2023,"date_issued":"2023-08","date_published":"2023-08","updated_at":"2026-07-22T22:24:57Z","subjects":["Cache","Memory Organization","Education","Assessments","Misconceptions"],"languages":["en","eng"],"rights":["Copyright 2023 Muhammad Mahmood"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/121310","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Herman, Geoffrey","Zilles, Craig","Patel, Sanjay","Franklin, Diana"]},{"key":"dc:creator","label":"Author","values":["Mahmood, Muhammad Suleman"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2023-08","2023-06-21"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Cache","Memory Organization","Education","Assessments","Misconceptions"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2023 Muhammad Mahmood"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/121310"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01","The student, Muhammad Mahmood, accepted the attached license on 2023-06-20 at 12:48.","The student, Muhammad Mahmood, submitted this Dissertation for approval on 2023-06-20 at 13:18.","This Dissertation was approved for publication on 2023-06-21 at 15:22.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19435 on 2023-12-04 at 17:18:01","In modern computer systems, memory is organized in multiple layers with different sizes and performance characteristics. Cache memories are parts of this hierarchy that resides inside the processor. They play a crucial role in the performance of the memory system. They also have an important role in the security of computer programs. The ideas behind caches within processors translate directly to the caches implemented within database systems and large-scale web applications. Earlier studies have shown that students find it difficult to understand the operation of caches and how it affects the performance of the programs. It is important for students to understand how caches work so that they can understand the performance implications of their software design and learn how to mitigate the security issues related to caches. To improve students' understanding of caches, it is important to know what difficulties students face in understanding caches and why some concepts are difficult to understand. Knowing the stumbling blocks for students can help in designing methods and representations that can be helpful for students. This dissertation describes our efforts to investigate what difficulties students face in learning about caches and their performance implications within the context of an undergraduate computer architecture course. We also describe how computer administered cache assessments were developed and used to meet the challenges of growing enrollment in computer architecture course. We analyzed the exam questions related to caches where students had low scores to find what concepts the students were required to know for the exams. We then developed an assessment to gauge how well students know these concepts. We conducted think-aloud interviews with students to explore why students found some concepts difficult to comprehend. The analysis of these interviews led to the design of new representations for tracking the state of a cache. We also investigated the role of spatial ability in learning caches. This revealed that students with high spatial ability performed better in exams related to caches. We modified our instruction methods to reduce the impact of spatial ability by describing the operation of caches through an algorithmic approach. We discuss the methodology and results of these investigations in this dissertation. We also discuss the implications of these findings and how they may be used to further improve instruction of caches."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Analyzing and improving cache memory instruction"]}]}],"canonical_facts":{"dc:contributor":["Herman, Geoffrey","Zilles, Craig","Patel, Sanjay","Franklin, Diana"],"dc:creator":["Mahmood, Muhammad Suleman"],"dc:date":["2023-08","2023-06-21"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01","The student, Muhammad Mahmood, accepted the attached license on 2023-06-20 at 12:48.","The student, Muhammad Mahmood, submitted this Dissertation for approval on 2023-06-20 at 13:18.","This Dissertation was approved for publication on 2023-06-21 at 15:22.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19435 on 2023-12-04 at 17:18:01","In modern computer systems, memory is organized in multiple layers with different sizes and performance characteristics. Cache memories are parts of this hierarchy that resides inside the processor. They play a crucial role in the performance of the memory system. They also have an important role in the security of computer programs. The ideas behind caches within processors translate directly to the caches implemented within database systems and large-scale web applications. Earlier studies have shown that students find it difficult to understand the operation of caches and how it affects the performance of the programs. It is important for students to understand how caches work so that they can understand the performance implications of their software design and learn how to mitigate the security issues related to caches. To improve students' understanding of caches, it is important to know what difficulties students face in understanding caches and why some concepts are difficult to understand. Knowing the stumbling blocks for students can help in designing methods and representations that can be helpful for students. This dissertation describes our efforts to investigate what difficulties students face in learning about caches and their performance implications within the context of an undergraduate computer architecture course. We also describe how computer administered cache assessments were developed and used to meet the challenges of growing enrollment in computer architecture course. We analyzed the exam questions related to caches where students had low scores to find what concepts the students were required to know for the exams. We then developed an assessment to gauge how well students know these concepts. We conducted think-aloud interviews with students to explore why students found some concepts difficult to comprehend. The analysis of these interviews led to the design of new representations for tracking the state of a cache. We also investigated the role of spatial ability in learning caches. This revealed that students with high spatial ability performed better in exams related to caches. We modified our instruction methods to reduce the impact of spatial ability by describing the operation of caches through an algorithmic approach. We discuss the methodology and results of these investigations in this dissertation. We also discuss the implications of these findings and how they may be used to further improve instruction of caches."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/121310"],"dc:language":["en","eng"],"dc:rights":["Copyright 2023 Muhammad Mahmood"],"dc:subject":["Cache","Memory Organization","Education","Assessments","Misconceptions"],"dc:title":["Analyzing and improving cache memory instruction"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:57Z"}