{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/120387"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/120387","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Analysis of Data Streaming Accelerator in Intel Sapphire Rapids Xeon Scalable Processors","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-05-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-05-01","abstract_has_math":false,"creators":["Kuper, Reese"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kim, Nam Sung"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2023,"date_issued":"2023-05","date_published":"2023-05","updated_at":"2026-07-22T22:24:57Z","subjects":["Intel Dsa","On-chip Accelerators","Soc","Dma","Data Streaming","Hardware Accelerators"],"languages":["en","eng"],"rights":["Copyright 2023 Reese Kuper"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/120387","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kim, Nam Sung"]},{"key":"dc:creator","label":"Author","values":["Kuper, Reese"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2023-05","2023-05-03"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Intel Dsa","On-chip Accelerators","Soc","Dma","Data Streaming","Hardware Accelerators"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2023 Reese Kuper"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/120387"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-05-01","The student, Reese Kuper, accepted the attached license on 2023-05-02 at 17:16.","The student, Reese Kuper, submitted this Thesis for approval on 2023-05-02 at 17:26.","This Thesis was approved for publication on 2023-05-03 at 09:37.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19044 on 2023-09-01 at 17:13:42","As the semiconductor power density is no longer constant with the technology process scaling down, modern CPUs are integrating capable data accelerators on chip, aiming to improve performance and efficiency for a wide range of applications and usages. One such accelerator is the Intel Data Streaming Accelerator (Intel DSA) introduced in Intel 4th Generation Xeon Scalable CPUs (Sapphire Rapids). Intel DSA targets data movement operations in memory that are common sources of overhead in datacenter workloads and infrastructure. In addition, it becomes much more versatile by supporting a wider range of operations on streaming data such as CRC32 calculations, delta record creation/merging, and data integrity field (DIF) operations. Several architectural innovations have also been made to facilitate the practical use of Intel DSA, for example, shared virtual memory (SVM) and new x86 instructions for lock-free work descriptor submission and synchronization. This thesis sets out to introduce the latest features supported by Intel DSA, deep-dive into its versatility, and analyze its throughput and performance benefits through a comprehensive evaluation. Our analysis demonstrates that Intel DSA saves CPU cycles by 37.3\\% and 71.3\\% when synchronously offloading 1~KB memory copy operations with batch sizes of 1 and 4, respectively, compared to their software counterpart (i.e., memcpy() running on a core). This allows cores to leverage precious cycles for more complex and latency-sensitive tasks rather than for such simple but repetitive operations. By offloading the same operations asynchronously with batch sizes of 1 and 4, Intel DSA provides 2.3x and 6.4x higher throughput than the software counterpart, respectively. In addition to these inherent benefits, we also demonstrate that Intel DSA effectively avoids the pollution of performance-critical resources (i.e. on-chip caches), and thus eliminates performance interference with other co-running memory-intensive/latency-sensitive applications. Along with the analysis of its characteristics, we explore various use cases that can benefit from Intel DSA - DPDK-based VirtIO, SPDK-based NVMe-oF, cloud data caching services, and HPC/ML frameworks - as well as describing other potential use cases. Finally, we provide several guidelines that will help users to effectively use the Intel DSA accelerator device."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Analysis of Data Streaming Accelerator in Intel Sapphire Rapids Xeon Scalable Processors"]}]}],"canonical_facts":{"dc:contributor":["Kim, Nam Sung"],"dc:creator":["Kuper, Reese"],"dc:date":["2023-05","2023-05-03"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-05-01","The student, Reese Kuper, accepted the attached license on 2023-05-02 at 17:16.","The student, Reese Kuper, submitted this Thesis for approval on 2023-05-02 at 17:26.","This Thesis was approved for publication on 2023-05-03 at 09:37.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19044 on 2023-09-01 at 17:13:42","As the semiconductor power density is no longer constant with the technology process scaling down, modern CPUs are integrating capable data accelerators on chip, aiming to improve performance and efficiency for a wide range of applications and usages. One such accelerator is the Intel Data Streaming Accelerator (Intel DSA) introduced in Intel 4th Generation Xeon Scalable CPUs (Sapphire Rapids). Intel DSA targets data movement operations in memory that are common sources of overhead in datacenter workloads and infrastructure. In addition, it becomes much more versatile by supporting a wider range of operations on streaming data such as CRC32 calculations, delta record creation/merging, and data integrity field (DIF) operations. Several architectural innovations have also been made to facilitate the practical use of Intel DSA, for example, shared virtual memory (SVM) and new x86 instructions for lock-free work descriptor submission and synchronization. This thesis sets out to introduce the latest features supported by Intel DSA, deep-dive into its versatility, and analyze its throughput and performance benefits through a comprehensive evaluation. Our analysis demonstrates that Intel DSA saves CPU cycles by 37.3\\% and 71.3\\% when synchronously offloading 1~KB memory copy operations with batch sizes of 1 and 4, respectively, compared to their software counterpart (i.e., memcpy() running on a core). This allows cores to leverage precious cycles for more complex and latency-sensitive tasks rather than for such simple but repetitive operations. By offloading the same operations asynchronously with batch sizes of 1 and 4, Intel DSA provides 2.3x and 6.4x higher throughput than the software counterpart, respectively. In addition to these inherent benefits, we also demonstrate that Intel DSA effectively avoids the pollution of performance-critical resources (i.e. on-chip caches), and thus eliminates performance interference with other co-running memory-intensive/latency-sensitive applications. Along with the analysis of its characteristics, we explore various use cases that can benefit from Intel DSA - DPDK-based VirtIO, SPDK-based NVMe-oF, cloud data caching services, and HPC/ML frameworks - as well as describing other potential use cases. Finally, we provide several guidelines that will help users to effectively use the Intel DSA accelerator device."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/120387"],"dc:language":["en","eng"],"dc:rights":["Copyright 2023 Reese Kuper"],"dc:subject":["Intel Dsa","On-chip Accelerators","Soc","Dma","Data Streaming","Hardware Accelerators"],"dc:title":["Analysis of Data Streaming Accelerator in Intel Sapphire Rapids Xeon Scalable Processors"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:57Z"}