{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/120249"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/120249","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Reducing communication bottlenecks in iterative solvers","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms","abstract_has_math":false,"creators":["Lockhart, Shelby"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Olson, Luke N","Gropp, William D","Solomonik, Edgar","Swirydowicz, Katarzyna"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2023,"date_issued":"2023-05","date_published":"2023-05","updated_at":"2026-07-22T22:24:57Z","subjects":["Performance Modeling","Gpu","Cpu","Data Movement","Cuda-aware","Gpudirect","Mpi","Parallel","Communication","Sparse Matrix","Node-aware","Collectives","Low Synchronization","Orthogonalization","High Performance Computing"],"languages":["en","eng"],"rights":["Copyright 2023 Shelby Lockhart"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/120249","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Olson, Luke N","Gropp, William D","Solomonik, Edgar","Swirydowicz, Katarzyna"]},{"key":"dc:creator","label":"Author","values":["Lockhart, Shelby"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2023-05","2023-04-14"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Performance Modeling","Gpu","Cpu","Data Movement","Cuda-aware","Gpudirect","Mpi","Parallel","Communication","Sparse Matrix","Node-aware","Collectives","Low Synchronization","Orthogonalization","High Performance Computing"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2023 Shelby Lockhart"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/120249"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms","The student, Shelby Lockhart, accepted the attached license on 2023-04-11 at 09:18.","The student, Shelby Lockhart, submitted this Dissertation for approval on 2023-04-11 at 09:30.","This Dissertation was approved for publication on 2023-04-14 at 13:50.","DSpace SAF Submission Ingestion Package generated from Vireo submission #18945 on 2023-09-01 at 17:08:12","This work focuses on reducing communication bottlenecks in iterative solvers, specifically, communication bottlenecks associated with the advent of modern high performance computing architectures. Communication bottlenecks can be the result of irregular point-to-point communication or high synchronization costs across all participating processes. There are two ways to address these communication bottlenecks, namely, alterations to the parallel implementation of communication within a given operation or algorithmic changes to reduce communication in an algorithm by performing mathematically equivalent operations that require less communication. A novel node-aware communication technique that takes advantage of the high-bandwidth interconnects and high CPU core counts on modern supercomputers is presented, which demonstrates improved performance for irregular point-to-point communication for both distributed inter-CPU and inter-GPU communication when communicating large data volumes. The technique is used in the design of a communication efficient enlarged conjugate gradient method implemented within a CPU-based parallel solver. Additionally, the technique is used to reduce communication costs in the unstructured mesh boundary exchanges in MIRGE-Com, a GPU-based codebase for solving the compressible Navier-Stokes equations for viscous flows, and the Euler equations for inviscid flows of reactive fluid mixtures within the Center for Exascale Enabled Scramjet Design. Recent research introduced low synchronization orthogonalization routines within the context of generalized minimum residual methods, demonstrating the power of re-writing solvers to take advantage of mathematically equivalent operations that decompose into more distributed-computing friendly kernels. A performance study of these low synchronization orthogonalization routines extended to Anderson acceleration is presented, demonstrating a reduction in synchronization cost for the method in both distributed CPU and GPU computing environments. Furthermore, an analysis of recent Anderson acceleration variants, alternating Anderson acceleration and composite Anderson acceleration, and the extension of low synchronization orthogonalization techniques to composite Anderson acceleration is included. Importantly, considerations for the development of performant Anderson acceleration solvers on emerging supercomputer architectures are discussed. In sum, this work contributes strategies for reducing communication bottlenecks in iterative solvers which take into consideration the underlying architecture of high performance computing systems. Techniques utilizing restructured message passing and updated mathematical algorithms which require less costly communication are presented."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Reducing communication bottlenecks in iterative solvers"]}]}],"canonical_facts":{"dc:contributor":["Olson, Luke N","Gropp, William D","Solomonik, Edgar","Swirydowicz, Katarzyna"],"dc:creator":["Lockhart, Shelby"],"dc:date":["2023-05","2023-04-14"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms","The student, Shelby Lockhart, accepted the attached license on 2023-04-11 at 09:18.","The student, Shelby Lockhart, submitted this Dissertation for approval on 2023-04-11 at 09:30.","This Dissertation was approved for publication on 2023-04-14 at 13:50.","DSpace SAF Submission Ingestion Package generated from Vireo submission #18945 on 2023-09-01 at 17:08:12","This work focuses on reducing communication bottlenecks in iterative solvers, specifically, communication bottlenecks associated with the advent of modern high performance computing architectures. Communication bottlenecks can be the result of irregular point-to-point communication or high synchronization costs across all participating processes. There are two ways to address these communication bottlenecks, namely, alterations to the parallel implementation of communication within a given operation or algorithmic changes to reduce communication in an algorithm by performing mathematically equivalent operations that require less communication. A novel node-aware communication technique that takes advantage of the high-bandwidth interconnects and high CPU core counts on modern supercomputers is presented, which demonstrates improved performance for irregular point-to-point communication for both distributed inter-CPU and inter-GPU communication when communicating large data volumes. The technique is used in the design of a communication efficient enlarged conjugate gradient method implemented within a CPU-based parallel solver. Additionally, the technique is used to reduce communication costs in the unstructured mesh boundary exchanges in MIRGE-Com, a GPU-based codebase for solving the compressible Navier-Stokes equations for viscous flows, and the Euler equations for inviscid flows of reactive fluid mixtures within the Center for Exascale Enabled Scramjet Design. Recent research introduced low synchronization orthogonalization routines within the context of generalized minimum residual methods, demonstrating the power of re-writing solvers to take advantage of mathematically equivalent operations that decompose into more distributed-computing friendly kernels. A performance study of these low synchronization orthogonalization routines extended to Anderson acceleration is presented, demonstrating a reduction in synchronization cost for the method in both distributed CPU and GPU computing environments. Furthermore, an analysis of recent Anderson acceleration variants, alternating Anderson acceleration and composite Anderson acceleration, and the extension of low synchronization orthogonalization techniques to composite Anderson acceleration is included. Importantly, considerations for the development of performant Anderson acceleration solvers on emerging supercomputer architectures are discussed. In sum, this work contributes strategies for reducing communication bottlenecks in iterative solvers which take into consideration the underlying architecture of high performance computing systems. Techniques utilizing restructured message passing and updated mathematical algorithms which require less costly communication are presented."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/120249"],"dc:language":["en","eng"],"dc:rights":["Copyright 2023 Shelby Lockhart"],"dc:subject":["Performance Modeling","Gpu","Cpu","Data Movement","Cuda-aware","Gpudirect","Mpi","Parallel","Communication","Sparse Matrix","Node-aware","Collectives","Low Synchronization","Orthogonalization","High Performance Computing"],"dc:title":["Reducing communication bottlenecks in iterative solvers"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:57Z"}