{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/120158"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/120158","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"FSSD-DPR: FPGA-based emulation framework for solid-state drives with dynamic parameter-based reconfiguration","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms","abstract_has_math":false,"creators":["Lu, Yizhen"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chen, Deming"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2023,"date_issued":"2023-05","date_published":"2023-05","updated_at":"2026-07-22T22:24:56Z","subjects":["Ssd Emulator","Fpga","Design Space Exploration","Runtime Reconfiguration"],"languages":["en","eng"],"rights":["Copyright 2023 Yizhen Lu"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/120158","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chen, Deming"]},{"key":"dc:creator","label":"Author","values":["Lu, Yizhen"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2023-05","2023-05-02"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Ssd Emulator","Fpga","Design Space Exploration","Runtime Reconfiguration"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2023 Yizhen Lu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/120158"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms","The student, Yizhen Lu, accepted the attached license on 2023-05-02 at 01:09.","The student, Yizhen Lu, submitted this Thesis for approval on 2023-05-02 at 01:10.","This Thesis was approved for publication on 2023-05-02 at 12:47.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19290 on 2023-09-01 at 16:56:06","Solid State Drives (SSDs) have become a popular choice for storage in both consumer and enterprise markets due to their superior access latency and bandwidth compared to Hard Disk Drives (HDDs). However, to fully leverage the benefits of SSDs, systems researchers need to understand how the design and microarchitecture of the SSD impact end-to-end application performance. Unfortunately, most studies treating SSDs as fixed black-box components cannot generate these insights. Furthermore, purchasing multiple SSDs to understand these relationships is both expensive in cost and labor and ineffective, since the underlying SSD microarchitecture is unknown to the system designer. Currently, the most popular method to study SSDs is via simulators. However, such simulators are completely software-based and do not have any real data transfers. They cannot simulate the latency coming from Non-Volatile Memory Express (NVMe) and Peripheral Component Interconnect Express (PCIe) interfaces. To address these issues, we present FSSD, an FPGA-based emulation system that models the latency and access patterns of an actual NVMe SSD to demonstrate how the microarchitecture affects performance. FSSD takes advantage of the flexibility of an FPGA, enabling users to customize SSD microarchitecture features and perform design space exploration of SSD for data-intensive applications. Evaluations show that it provides over 1000x speedup than running benchmarks using software-based simulation like SimpleSSD. The ability to customize SSD parameters and emulate NAND latency with high precision makes FSSD an invaluable tool for SSD research and development. The thesis introduces a novel Dynamic Parameter-based Reconfiguration (DPR) scheme into the FSSD design, which includes parameter overwrite for more efficient reconfiguration. FSSD-DPR saves time when dealing with tasks like Design Space Exploration (DSE) by only requiring synthesis when first deployed. FSSD-DPR provides a better platform for comprehensive design space exploration of SSD microarchitectures for data-intensive applications. The DPR extension facilitates users to study various aspects of SSD design and microarchitecture, including NAND Flash and memory access patterns, wear-leveling techniques, and garbage collection algorithms. Overall, FSSD-DPR aims to contribute to SSD research and advance SSD development by focusing on studying SSD microarchitecture and its impact on end-to-end application performance."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["FSSD-DPR: FPGA-based emulation framework for solid-state drives with dynamic parameter-based reconfiguration"]}]}],"canonical_facts":{"dc:contributor":["Chen, Deming"],"dc:creator":["Lu, Yizhen"],"dc:date":["2023-05","2023-05-02"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-09-01 without embargo terms","The student, Yizhen Lu, accepted the attached license on 2023-05-02 at 01:09.","The student, Yizhen Lu, submitted this Thesis for approval on 2023-05-02 at 01:10.","This Thesis was approved for publication on 2023-05-02 at 12:47.","DSpace SAF Submission Ingestion Package generated from Vireo submission #19290 on 2023-09-01 at 16:56:06","Solid State Drives (SSDs) have become a popular choice for storage in both consumer and enterprise markets due to their superior access latency and bandwidth compared to Hard Disk Drives (HDDs). However, to fully leverage the benefits of SSDs, systems researchers need to understand how the design and microarchitecture of the SSD impact end-to-end application performance. Unfortunately, most studies treating SSDs as fixed black-box components cannot generate these insights. Furthermore, purchasing multiple SSDs to understand these relationships is both expensive in cost and labor and ineffective, since the underlying SSD microarchitecture is unknown to the system designer. Currently, the most popular method to study SSDs is via simulators. However, such simulators are completely software-based and do not have any real data transfers. They cannot simulate the latency coming from Non-Volatile Memory Express (NVMe) and Peripheral Component Interconnect Express (PCIe) interfaces. To address these issues, we present FSSD, an FPGA-based emulation system that models the latency and access patterns of an actual NVMe SSD to demonstrate how the microarchitecture affects performance. FSSD takes advantage of the flexibility of an FPGA, enabling users to customize SSD microarchitecture features and perform design space exploration of SSD for data-intensive applications. Evaluations show that it provides over 1000x speedup than running benchmarks using software-based simulation like SimpleSSD. The ability to customize SSD parameters and emulate NAND latency with high precision makes FSSD an invaluable tool for SSD research and development. The thesis introduces a novel Dynamic Parameter-based Reconfiguration (DPR) scheme into the FSSD design, which includes parameter overwrite for more efficient reconfiguration. FSSD-DPR saves time when dealing with tasks like Design Space Exploration (DSE) by only requiring synthesis when first deployed. FSSD-DPR provides a better platform for comprehensive design space exploration of SSD microarchitectures for data-intensive applications. The DPR extension facilitates users to study various aspects of SSD design and microarchitecture, including NAND Flash and memory access patterns, wear-leveling techniques, and garbage collection algorithms. Overall, FSSD-DPR aims to contribute to SSD research and advance SSD development by focusing on studying SSD microarchitecture and its impact on end-to-end application performance."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/120158"],"dc:language":["en","eng"],"dc:rights":["Copyright 2023 Yizhen Lu"],"dc:subject":["Ssd Emulator","Fpga","Design Space Exploration","Runtime Reconfiguration"],"dc:title":["FSSD-DPR: FPGA-based emulation framework for solid-state drives with dynamic parameter-based reconfiguration"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:56Z"}