{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/115759"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/115759","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Stability analysis of voltage-in-current latency insertion method","abstract":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01","abstract_html":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01","abstract_has_math":false,"creators":["Wang, Qingyi"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Schutt-Ainé, José E"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2022,"date_issued":"2022-05","date_published":"2022-05","updated_at":"2026-07-22T22:24:55Z","subjects":["Latency insertion methods","Circuit simulation"],"languages":["en","eng"],"rights":["Copyright 2022 Qingyi Wang"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/115759","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Schutt-Ainé, José E"]},{"key":"dc:creator","label":"Author","values":["Wang, Qingyi"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2022-05","2022-04-29"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Latency insertion methods","Circuit simulation"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2022 Qingyi Wang"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/115759"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01","The student, Qingyi Wang, accepted the attached license on 2022-04-29 at 15:10.","The student, Qingyi Wang, submitted this Thesis for approval on 2022-04-29 at 15:13.","This Thesis was approved for publication on 2022-04-29 at 15:22.","DSpace SAF Submission Ingestion Package generated from Vireo submission #18017 on 2022-11-11 at 12:58:18","As the semiconductor industry produces more transistors with higher frequencies and a more compact chip design, the demand for a novel simulation tool capable of simulating large-scale circuits both quickly and accurately has been increasing. The latency insertion method (LIM) has been proposed as a viable alternative to the conventional SPICE simulator for the simulation of large networks as it enables linear numerical complexity and achieves significant speed improvement. In this thesis, an improved version of the LIM called the voltage-in-current latency insertion method (VinC LIM) is discussed. Special attention is devoted to the stability analysis of VinC LIM. We prove and demonstrate that VinC LIM overcomes the time step size limitation that the basic LIM faces and improves the stability significantly. With the larger time steps, VinC LIM can allow the simulation to finish in a much shorter time without suffering from the stability limitation."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Stability analysis of voltage-in-current latency insertion method"]}]}],"canonical_facts":{"dc:contributor":["Schutt-Ainé, José E"],"dc:creator":["Wang, Qingyi"],"dc:date":["2022-05","2022-04-29"],"dc:description":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01","The student, Qingyi Wang, accepted the attached license on 2022-04-29 at 15:10.","The student, Qingyi Wang, submitted this Thesis for approval on 2022-04-29 at 15:13.","This Thesis was approved for publication on 2022-04-29 at 15:22.","DSpace SAF Submission Ingestion Package generated from Vireo submission #18017 on 2022-11-11 at 12:58:18","As the semiconductor industry produces more transistors with higher frequencies and a more compact chip design, the demand for a novel simulation tool capable of simulating large-scale circuits both quickly and accurately has been increasing. The latency insertion method (LIM) has been proposed as a viable alternative to the conventional SPICE simulator for the simulation of large networks as it enables linear numerical complexity and achieves significant speed improvement. In this thesis, an improved version of the LIM called the voltage-in-current latency insertion method (VinC LIM) is discussed. Special attention is devoted to the stability analysis of VinC LIM. We prove and demonstrate that VinC LIM overcomes the time step size limitation that the basic LIM faces and improves the stability significantly. With the larger time steps, VinC LIM can allow the simulation to finish in a much shorter time without suffering from the stability limitation."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/115759"],"dc:language":["en","eng"],"dc:rights":["Copyright 2022 Qingyi Wang"],"dc:subject":["Latency insertion methods","Circuit simulation"],"dc:title":["Stability analysis of voltage-in-current latency insertion method"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:55Z"}