{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/115685"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/115685","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Efficient memory access in modern accelerators","abstract":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01","abstract_html":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01","abstract_has_math":false,"creators":["Asgharimoghaddam, Hadi"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Fletcher, Christopher","Emer, Joel","Kumar, Rakesh","Patel, Sanjay","Solomonik, Edgar"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2022,"date_issued":"2022-05","date_published":"2022-05","updated_at":"2026-07-22T22:24:55Z","subjects":["Computer Architecture","Memory Systems","3D Die-Stacking","Sparse Tensor Algebra","Sparse Accelerators","Dynamic Tiling"],"languages":["en","eng"],"rights":["Copyright 2022 Hadi Asgharimoghaddam"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/115685","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Fletcher, Christopher","Emer, Joel","Kumar, Rakesh","Patel, Sanjay","Solomonik, Edgar"]},{"key":"dc:creator","label":"Author","values":["Asgharimoghaddam, Hadi"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2022-05","2022-04-08"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Architecture","Memory Systems","3D Die-Stacking","Sparse Tensor Algebra","Sparse Accelerators","Dynamic Tiling"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2022 Hadi Asgharimoghaddam"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/115685"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01","The student, Hadi Asgharimoghaddam, accepted the attached license on 2022-04-07 at 23:36.","The student, Hadi Asgharimoghaddam, submitted this Dissertation for approval on 2022-04-07 at 23:52.","This Dissertation was approved for publication on 2022-04-08 at 15:50.","DSpace SAF Submission Ingestion Package generated from Vireo submission #17608 on 2022-11-11 at 12:18:56","This dissertation examines various methods of narrowing the performance gap between the main memory and processing units in accelerators. We divide approaches into two categories of improving the main memory system performance and reducing reliance on memory. Then, we offer novel techniques to address each group of approaches. To improve the performance of the memory system, first, we investigate near-DRAM acceleration. In this approach, the processing unit dies are stacked on top of dynamic random access memory (DRAM) dies through 3D die-stacking technology resulting in a power-efficient higher aggregate bandwidth memory system. Second, we propose in-buffer processing as an alternative to 3D die-stacking technology. In this solution, we place accelerators in data buffers of load-reduced dual inline memory module (LRDIMM) memory, which is originally developed to support large memory systems for servers, to avoid relying on 3D/2.5D die stacking. To reduce reliance on the memory system, we investigate various optimizations pertaining to sparse data orchestration. First, we propose hierarchical intersection to eliminate ineffectual data fetch and computation in sparse tensor algebra. Second, we investigate data orchestration, specifically dynamic tiling, in sparse matrix multiplication (SpMSpM) to reduce main memory traffic. Finally, we propose a generalized dynamic tiling and data orchestration mechanism for sparse tensor algebra. We present our generalized data orchestration unit as a generic primitive that can be integrated into accelerators with arbitrary dataflow, encompassing all the optimizations we proposed to reduce reliance on the memory system. This dissertation offers various mechanisms to overcome the memory access bottlenecks resulting in a holistic solution for efficient memory access in modern accelerators."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Efficient memory access in modern accelerators"]}]}],"canonical_facts":{"dc:contributor":["Fletcher, Christopher","Emer, Joel","Kumar, Rakesh","Patel, Sanjay","Solomonik, Edgar"],"dc:creator":["Asgharimoghaddam, Hadi"],"dc:date":["2022-05","2022-04-08"],"dc:description":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01","The student, Hadi Asgharimoghaddam, accepted the attached license on 2022-04-07 at 23:36.","The student, Hadi Asgharimoghaddam, submitted this Dissertation for approval on 2022-04-07 at 23:52.","This Dissertation was approved for publication on 2022-04-08 at 15:50.","DSpace SAF Submission Ingestion Package generated from Vireo submission #17608 on 2022-11-11 at 12:18:56","This dissertation examines various methods of narrowing the performance gap between the main memory and processing units in accelerators. We divide approaches into two categories of improving the main memory system performance and reducing reliance on memory. Then, we offer novel techniques to address each group of approaches. To improve the performance of the memory system, first, we investigate near-DRAM acceleration. In this approach, the processing unit dies are stacked on top of dynamic random access memory (DRAM) dies through 3D die-stacking technology resulting in a power-efficient higher aggregate bandwidth memory system. Second, we propose in-buffer processing as an alternative to 3D die-stacking technology. In this solution, we place accelerators in data buffers of load-reduced dual inline memory module (LRDIMM) memory, which is originally developed to support large memory systems for servers, to avoid relying on 3D/2.5D die stacking. To reduce reliance on the memory system, we investigate various optimizations pertaining to sparse data orchestration. First, we propose hierarchical intersection to eliminate ineffectual data fetch and computation in sparse tensor algebra. Second, we investigate data orchestration, specifically dynamic tiling, in sparse matrix multiplication (SpMSpM) to reduce main memory traffic. Finally, we propose a generalized dynamic tiling and data orchestration mechanism for sparse tensor algebra. We present our generalized data orchestration unit as a generic primitive that can be integrated into accelerators with arbitrary dataflow, encompassing all the optimizations we proposed to reduce reliance on the memory system. This dissertation offers various mechanisms to overcome the memory access bottlenecks resulting in a holistic solution for efficient memory access in modern accelerators."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/115685"],"dc:language":["en","eng"],"dc:rights":["Copyright 2022 Hadi Asgharimoghaddam"],"dc:subject":["Computer Architecture","Memory Systems","3D Die-Stacking","Sparse Tensor Algebra","Sparse Accelerators","Dynamic Tiling"],"dc:title":["Efficient memory access in modern accelerators"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:55Z"}