{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/115624"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/115624","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"A procedure for tightly integrating accelerators into out-of-order processors","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2024-05-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2024-05-01","abstract_has_math":false,"creators":["Jin, Robert"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["‪Kim, Nam Sung"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2022,"date_issued":"2022-05","date_published":"2022-05","updated_at":"2026-07-22T22:24:54Z","subjects":["accelerator","out-of-order processor"],"languages":["en","eng"],"rights":["Copyright 2022 Robert Jin"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/115624","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["‪Kim, Nam Sung"]},{"key":"dc:creator","label":"Author","values":["Jin, Robert"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2022-05","2022-04-29"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["accelerator","out-of-order processor"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2022 Robert Jin"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/115624"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2024-05-01","The student, Robert Jin, accepted the attached license on 2022-04-28 at 16:27.","The student, Robert Jin, submitted this Thesis for approval on 2022-04-28 at 16:40.","This Thesis was approved for publication on 2022-04-29 at 15:30.","DSpace SAF Submission Ingestion Package generated from Vireo submission #17997 on 2022-11-11 at 12:12:18","It is no secret that hardware accelerators are commonly used today to accelerate a wide range of application domains from machine learning to graph processing. Efficient as they are, these accelerators are not standalone and generally serve as a co-processor integrated in some fashion to the main CPU of the system. Accelerator integration can be broadly categorized as on-CPU (tightly-coupled) or off-CPU (loosely-coupled). Methods of off-CPU integration with the accelerator residing on a system bus or interconnect are generally well-explored and already developed today with a host of existing industry standards and protocols. This work tackles the problem of in-CPU integration, which is more complex and intrusive as it requires modification of the CPU itself, but in turn allows low latency data transfer. Our goal is to propose a procedure that generalizes an approach that makes the CPU-tight integration process simplified and reusable for typical out-of-order processors. We introduce a CPU-accelerator hardware interface that allows customization of communication, data transfer, and resource sharing depending on specific accelerator needs. Specifically, this interface allows for low latency communication, register sharing, and simplified control transfer to ensure correct execution. Our interface is implemented on an out-of-order RSD core for evaluation, and then we study how different types of accelerators will use this interface to communicate with the CPU."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["A procedure for tightly integrating accelerators into out-of-order processors"]}]}],"canonical_facts":{"dc:contributor":["‪Kim, Nam Sung"],"dc:creator":["Jin, Robert"],"dc:date":["2022-05","2022-04-29"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2024-05-01","The student, Robert Jin, accepted the attached license on 2022-04-28 at 16:27.","The student, Robert Jin, submitted this Thesis for approval on 2022-04-28 at 16:40.","This Thesis was approved for publication on 2022-04-29 at 15:30.","DSpace SAF Submission Ingestion Package generated from Vireo submission #17997 on 2022-11-11 at 12:12:18","It is no secret that hardware accelerators are commonly used today to accelerate a wide range of application domains from machine learning to graph processing. Efficient as they are, these accelerators are not standalone and generally serve as a co-processor integrated in some fashion to the main CPU of the system. Accelerator integration can be broadly categorized as on-CPU (tightly-coupled) or off-CPU (loosely-coupled). Methods of off-CPU integration with the accelerator residing on a system bus or interconnect are generally well-explored and already developed today with a host of existing industry standards and protocols. This work tackles the problem of in-CPU integration, which is more complex and intrusive as it requires modification of the CPU itself, but in turn allows low latency data transfer. Our goal is to propose a procedure that generalizes an approach that makes the CPU-tight integration process simplified and reusable for typical out-of-order processors. We introduce a CPU-accelerator hardware interface that allows customization of communication, data transfer, and resource sharing depending on specific accelerator needs. Specifically, this interface allows for low latency communication, register sharing, and simplified control transfer to ensure correct execution. Our interface is implemented on an out-of-order RSD core for evaluation, and then we study how different types of accelerators will use this interface to communicate with the CPU."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/115624"],"dc:language":["en","eng"],"dc:rights":["Copyright 2022 Robert Jin"],"dc:subject":["accelerator","out-of-order processor"],"dc:title":["A procedure for tightly integrating accelerators into out-of-order processors"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:54Z"}