{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/115489"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/115489","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Fine-grained memory access over I/O interconnect for efficient remote sparse data access","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-11 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-11 without embargo terms","abstract_has_math":false,"creators":["Min, Seung Won"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hwu, Wen-mei","Chen, Deming","Chung, I-hsin","Huang, Jian","Patel, Sanjay"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2022,"date_issued":"2022-05","date_published":"2022-05","updated_at":"2026-07-22T22:24:54Z","subjects":["data access efficiency","large-scale dataset","sparse memory access"],"languages":["en","eng"],"rights":["Copyright 2022 Seung Won Min"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/115489","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hwu, Wen-mei","Chen, Deming","Chung, I-hsin","Huang, Jian","Patel, Sanjay"]},{"key":"dc:creator","label":"Author","values":["Min, Seung Won"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2022-05","2022-04-19"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["data access efficiency","large-scale dataset","sparse memory access"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2022 Seung Won Min"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/115489"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-11 without embargo terms","The student, Seung Won Min, accepted the attached license on 2022-04-19 at 04:46.","The student, Seung Won Min, submitted this Dissertation for approval on 2022-04-19 at 04:47.","This Dissertation was approved for publication on 2022-04-19 at 16:58.","DSpace SAF Submission Ingestion Package generated from Vireo submission #17779 on 2022-11-11 at 13:15:43","The combination of the growing size and complexity of application datasets is introducing a new challenge to accelerators. The growing size of datasets forces us to place them in a larger CPU memory, and the growing complexity of datasets introduces more irregularity in data access patterns. However, the existing data transfer mechanisms are optimized toward transferring regular and densely accessed datasets, and not for the complex and sparse datasets. With the existing methods, now the accelerators often spend more time accessing complex datasets stored in CPU memory rather than actually doing the computation. To overcome the limitations of the existing data transfer mechanisms, this dissertation proposes to utilize many fine-grained memory accesses over I/O interconnect, such as the industry standard PCIe, instead of the traditional coarse-grained block data transfer method. While the fine-grained memory access over I/O interconnect poses a danger of introducing high per-packet overhead, the benefit from its flexibility in accessing complex data structures can outweigh the overhead. To accurately evaluate the overhead and benefit of the fine-grained memory access over I/O interconnect, we begin by developing a methodology to directly analyze I/O traffic. While the direct I/O level analysis is not a prevalent approach in the current academic research, the existing indirect application-level analysis approach is insufficient to fully capture the intricacy of I/O behaviors. We fill this gap by designing our own custom I/O analyzer using a field-programmable gate array (FPGA) and demonstrate how the potential overhead of the fine-grained access over I/O interconnect can be identified and avoided. Based on the insights we gained from the analysis, we redesign and optimize several real-world applications using the fine-grained memory access over I/O interconnect and show that we can speed up the applications several times over the existing methods. Next, this dissertation addresses the question of integrating the fine-grained memory access over I/O interconnect into the existing software development environment. Since most programmers may not have a deep hardware-level understanding of the fine-grained memory access over I/O interconnect, it is necessary to abstract away any optimizations that require deep understanding of the hardware and provide these optimizations in libraries and frameworks. To achieve this goal, in our work, we abstract away the hardware-level optimizations behind our custom array class called UnifiedTensor, and transparently apply the optimizations whenever remote memory accesses are done through this class. With the help of the abstraction, only about 2-3 lines of code modifications are sufficient to fully utilize our method for most of the existing programs. At the same time, we also provide a flexible development environment to enable quick deployment of new hardware optimizations for the framework developers. Finally, we conclude this dissertation by proposing a flexible data tiering strategy in modern systems with the fine-grained memory access over I/O interconnect. While there are multiple tiers of memory in modern computer systems, currently partitioning sparse datasets over multiple tiers of memory and seamlessly accessing them in applications requires a lot of programming effort. To overcome the programming difficulty, we unify all data access methods to different tiers of memory with the fine-grained memory access over I/O interconnect. This not only keeps the overall application structure concise but also allows the programmers to quickly try out different data partitioning strategies in favor of achieving better data locality."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Fine-grained memory access over I/O interconnect for efficient remote sparse data access"]}]}],"canonical_facts":{"dc:contributor":["Hwu, Wen-mei","Chen, Deming","Chung, I-hsin","Huang, Jian","Patel, Sanjay"],"dc:creator":["Min, Seung Won"],"dc:date":["2022-05","2022-04-19"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-11 without embargo terms","The student, Seung Won Min, accepted the attached license on 2022-04-19 at 04:46.","The student, Seung Won Min, submitted this Dissertation for approval on 2022-04-19 at 04:47.","This Dissertation was approved for publication on 2022-04-19 at 16:58.","DSpace SAF Submission Ingestion Package generated from Vireo submission #17779 on 2022-11-11 at 13:15:43","The combination of the growing size and complexity of application datasets is introducing a new challenge to accelerators. The growing size of datasets forces us to place them in a larger CPU memory, and the growing complexity of datasets introduces more irregularity in data access patterns. However, the existing data transfer mechanisms are optimized toward transferring regular and densely accessed datasets, and not for the complex and sparse datasets. With the existing methods, now the accelerators often spend more time accessing complex datasets stored in CPU memory rather than actually doing the computation. To overcome the limitations of the existing data transfer mechanisms, this dissertation proposes to utilize many fine-grained memory accesses over I/O interconnect, such as the industry standard PCIe, instead of the traditional coarse-grained block data transfer method. While the fine-grained memory access over I/O interconnect poses a danger of introducing high per-packet overhead, the benefit from its flexibility in accessing complex data structures can outweigh the overhead. To accurately evaluate the overhead and benefit of the fine-grained memory access over I/O interconnect, we begin by developing a methodology to directly analyze I/O traffic. While the direct I/O level analysis is not a prevalent approach in the current academic research, the existing indirect application-level analysis approach is insufficient to fully capture the intricacy of I/O behaviors. We fill this gap by designing our own custom I/O analyzer using a field-programmable gate array (FPGA) and demonstrate how the potential overhead of the fine-grained access over I/O interconnect can be identified and avoided. Based on the insights we gained from the analysis, we redesign and optimize several real-world applications using the fine-grained memory access over I/O interconnect and show that we can speed up the applications several times over the existing methods. Next, this dissertation addresses the question of integrating the fine-grained memory access over I/O interconnect into the existing software development environment. Since most programmers may not have a deep hardware-level understanding of the fine-grained memory access over I/O interconnect, it is necessary to abstract away any optimizations that require deep understanding of the hardware and provide these optimizations in libraries and frameworks. To achieve this goal, in our work, we abstract away the hardware-level optimizations behind our custom array class called UnifiedTensor, and transparently apply the optimizations whenever remote memory accesses are done through this class. With the help of the abstraction, only about 2-3 lines of code modifications are sufficient to fully utilize our method for most of the existing programs. At the same time, we also provide a flexible development environment to enable quick deployment of new hardware optimizations for the framework developers. Finally, we conclude this dissertation by proposing a flexible data tiering strategy in modern systems with the fine-grained memory access over I/O interconnect. While there are multiple tiers of memory in modern computer systems, currently partitioning sparse datasets over multiple tiers of memory and seamlessly accessing them in applications requires a lot of programming effort. To overcome the programming difficulty, we unify all data access methods to different tiers of memory with the fine-grained memory access over I/O interconnect. This not only keeps the overall application structure concise but also allows the programmers to quickly try out different data partitioning strategies in favor of achieving better data locality."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/115489"],"dc:language":["en","eng"],"dc:rights":["Copyright 2022 Seung Won Min"],"dc:subject":["data access efficiency","large-scale dataset","sparse memory access"],"dc:title":["Fine-grained memory access over I/O interconnect for efficient remote sparse data access"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:54Z"}