{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/115330"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/115330","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Re-examining dual path processing","abstract":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-11 without embargo terms","abstract_html":"Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-11 without embargo terms","abstract_has_math":false,"creators":["Venkit, Abishek"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kumar, Rakesh"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2022,"date_issued":"2022-05","date_published":"2022-05","updated_at":"2026-07-22T22:24:54Z","subjects":["branch prediction","computer architecture","dual path instruction processing","gem5"],"languages":["en","eng"],"rights":["Copyright 2022 Abishek Venkit"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/115330","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kumar, Rakesh"]},{"key":"dc:creator","label":"Author","values":["Venkit, Abishek"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2022-05","2022-01-28"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["branch prediction","computer architecture","dual path instruction processing","gem5"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2022 Abishek Venkit"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/115330"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-11 without embargo terms","The student, Abishek Venkit, accepted the attached license on 2022-01-27 at 12:23.","The student, Abishek Venkit, submitted this Thesis for approval on 2022-01-27 at 12:31.","This Thesis was approved for publication on 2022-01-28 at 15:25.","DSpace SAF Submission Ingestion Package generated from Vireo submission #17489 on 2022-11-11 at 13:04:17","Branch prediction has long been a heavily studied topic in computer architecture research. Modern branch predictors can achieve upwards of 98% prediction accuracy on many workloads. However, as CPU pipelines have become deeper to support higher clock frequencies, the branch misprediction penalty has increased greatly. Even with high-fidelity branch predictors, branch misprediction accounts for significant performance degradation. To combat this, many have proposed various forms of dual path processing. Dual path processing fetches (and potentially decodes, renames, and executes) instructions on two or more paths when a low-confidence branch is encountered. If the branch is mispredicted, the instructions on the alternate path can immediately be processed, reducing the misprediction penalty. This work re-evaluates the efficacy of dual path processing when paired with modern branch prediction, state-of-the-art confidence estimation, and a deep CPU pipeline. Power and area overheads are considered when designing an architecture to process instructions on multiple paths. We call this architecture Dual Front End (DuFE). Careful analysis of DuFE, branch predictors, and confidence estimators reveal that achieving significant performance gain via dual path processing at a low hardware cost is likely futile. With current confidence estimation schemes, the best-case scenario DuFE variant achieves a 2.87% performance gain with significant overheads."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Re-examining dual path processing"]}]}],"canonical_facts":{"dc:contributor":["Kumar, Rakesh"],"dc:creator":["Venkit, Abishek"],"dc:date":["2022-05","2022-01-28"],"dc:description":["Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-11 without embargo terms","The student, Abishek Venkit, accepted the attached license on 2022-01-27 at 12:23.","The student, Abishek Venkit, submitted this Thesis for approval on 2022-01-27 at 12:31.","This Thesis was approved for publication on 2022-01-28 at 15:25.","DSpace SAF Submission Ingestion Package generated from Vireo submission #17489 on 2022-11-11 at 13:04:17","Branch prediction has long been a heavily studied topic in computer architecture research. Modern branch predictors can achieve upwards of 98% prediction accuracy on many workloads. However, as CPU pipelines have become deeper to support higher clock frequencies, the branch misprediction penalty has increased greatly. Even with high-fidelity branch predictors, branch misprediction accounts for significant performance degradation. To combat this, many have proposed various forms of dual path processing. Dual path processing fetches (and potentially decodes, renames, and executes) instructions on two or more paths when a low-confidence branch is encountered. If the branch is mispredicted, the instructions on the alternate path can immediately be processed, reducing the misprediction penalty. This work re-evaluates the efficacy of dual path processing when paired with modern branch prediction, state-of-the-art confidence estimation, and a deep CPU pipeline. Power and area overheads are considered when designing an architecture to process instructions on multiple paths. We call this architecture Dual Front End (DuFE). Careful analysis of DuFE, branch predictors, and confidence estimators reveal that achieving significant performance gain via dual path processing at a low hardware cost is likely futile. With current confidence estimation schemes, the best-case scenario DuFE variant achieves a 2.87% performance gain with significant overheads."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/115330"],"dc:language":["en","eng"],"dc:rights":["Copyright 2022 Abishek Venkit"],"dc:subject":["branch prediction","computer architecture","dual path instruction processing","gem5"],"dc:title":["Re-examining dual path processing"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:54Z"}