{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/113066"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/113066","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"High-efficiency and high-usability heterogeneous hardware acceleration with FPGAs","abstract":"The student, Sitao Huang, submitted this Dissertation for approval on 2021-07-16 at 16:21.","abstract_html":"The student, Sitao Huang, submitted this Dissertation for approval on 2021-07-16 at 16:21.","abstract_has_math":false,"creators":["Huang, Sitao"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hwu, Wen-mei","Chen, Deming","Huang, Jian","Patel, Sanjay","Cong, Jason","Neuendorffer‬, ‪Stephen"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2022,"date_issued":"2022-01-12T21:46:53Z","date_published":"2022-01-12T21:46:53Z","updated_at":"2026-07-22T22:24:53Z","subjects":["FPGA","hardware acceleration","heterogeneous computing","high-level synthesis","compiler"],"languages":["en"],"rights":["Copyright 2021 Sitao Huang"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/113066","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hwu, Wen-mei","Chen, Deming","Huang, Jian","Patel, Sanjay","Cong, Jason","Neuendorffer‬, ‪Stephen"]},{"key":"dc:creator","label":"Author","values":["Huang, Sitao"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2022-01-12T21:46:53Z","2021-07-16","2021-08"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["FPGA","hardware acceleration","heterogeneous computing","high-level synthesis","compiler"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2021 Sitao Huang"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/113066"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The student, Sitao Huang, submitted this Dissertation for approval on 2021-07-16 at 16:21.","This Dissertation was approved for publication on 2021-07-16 at 16:35.","DSpace SAF Submission Ingestion Package generated from Vireo submission #16993 on 2022-01-12 at 12:46:09","Made available in DSpace on 2022-01-12T21:46:53Z (GMT). No. of bitstreams: 3 HUANG-DISSERTATION-2021.pdf: 4207597 bytes, checksum: 4bdbf5a78146b08049f1c3a48813093b (MD5) LICENSE.txt: 4208 bytes, checksum: b75d12c8fbce37303c927b111b8e5004 (MD5) PROQUEST_LICENSE.txt: 4554 bytes, checksum: 64b55b4a036f7c48c21dd799d551a503 (MD5) Previous issue date: 2021-07-16","The exploding complexity and computation efficiency requirements of applications are stimulating a strong demand for hardware acceleration with heterogeneous platforms that may contain CPUs, GPUs, FPGAs, ASICs, and other customized accelerators. Among these processors and hardware accelerators, field-programmable gate arrays (FPGAs) provide flexible programmability, low computation latency, as well as fine-grained parallel processing capability, and have demonstrated outstanding performance and flexibility in many applications and scenarios. However, a high-quality FPGA design is very hard to create and optimize as it requires FPGA expertise and a long design iteration time. In contrast, software applications are typically developed in a shorter development cycle, with high-level languages like Python, which is at a much higher level of abstraction than all existing hardware design languages. In this dissertation, we will first look into the basics of high-efficiency and high-usability FPGA accelerators in the heterogeneous hardware acceleration systems, including categories of accelerators, system architecture, design methodology, and so on. Secondly, we will discuss the optimization of heterogeneous systems that enables CPU-FPGA collaborative computing and improves system performance. Thirdly, we will look into our proposed high-level programming languages and optimization flows of FPGA accelerators, including language design, compiler design, optimization techniques, and so on. Finally, we will discuss how the proposed high-level programming and optimization flow can be used to program and optimize heterogeneous systems.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-01-12 without embargo terms","The student, Sitao Huang, accepted the attached license on 2021-07-16 at 16:13."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["High-efficiency and high-usability heterogeneous hardware acceleration with FPGAs"]}]}],"canonical_facts":{"dc:contributor":["Hwu, Wen-mei","Chen, Deming","Huang, Jian","Patel, Sanjay","Cong, Jason","Neuendorffer‬, ‪Stephen"],"dc:creator":["Huang, Sitao"],"dc:date":["2022-01-12T21:46:53Z","2021-07-16","2021-08"],"dc:description":["The student, Sitao Huang, submitted this Dissertation for approval on 2021-07-16 at 16:21.","This Dissertation was approved for publication on 2021-07-16 at 16:35.","DSpace SAF Submission Ingestion Package generated from Vireo submission #16993 on 2022-01-12 at 12:46:09","Made available in DSpace on 2022-01-12T21:46:53Z (GMT). No. of bitstreams: 3 HUANG-DISSERTATION-2021.pdf: 4207597 bytes, checksum: 4bdbf5a78146b08049f1c3a48813093b (MD5) LICENSE.txt: 4208 bytes, checksum: b75d12c8fbce37303c927b111b8e5004 (MD5) PROQUEST_LICENSE.txt: 4554 bytes, checksum: 64b55b4a036f7c48c21dd799d551a503 (MD5) Previous issue date: 2021-07-16","The exploding complexity and computation efficiency requirements of applications are stimulating a strong demand for hardware acceleration with heterogeneous platforms that may contain CPUs, GPUs, FPGAs, ASICs, and other customized accelerators. Among these processors and hardware accelerators, field-programmable gate arrays (FPGAs) provide flexible programmability, low computation latency, as well as fine-grained parallel processing capability, and have demonstrated outstanding performance and flexibility in many applications and scenarios. However, a high-quality FPGA design is very hard to create and optimize as it requires FPGA expertise and a long design iteration time. In contrast, software applications are typically developed in a shorter development cycle, with high-level languages like Python, which is at a much higher level of abstraction than all existing hardware design languages. In this dissertation, we will first look into the basics of high-efficiency and high-usability FPGA accelerators in the heterogeneous hardware acceleration systems, including categories of accelerators, system architecture, design methodology, and so on. Secondly, we will discuss the optimization of heterogeneous systems that enables CPU-FPGA collaborative computing and improves system performance. Thirdly, we will look into our proposed high-level programming languages and optimization flows of FPGA accelerators, including language design, compiler design, optimization techniques, and so on. Finally, we will discuss how the proposed high-level programming and optimization flow can be used to program and optimize heterogeneous systems.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-01-12 without embargo terms","The student, Sitao Huang, accepted the attached license on 2021-07-16 at 16:13."],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/113066"],"dc:language":["en"],"dc:rights":["Copyright 2021 Sitao Huang"],"dc:subject":["FPGA","hardware acceleration","heterogeneous computing","high-level synthesis","compiler"],"dc:title":["High-efficiency and high-usability heterogeneous hardware acceleration with FPGAs"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:53Z"}