{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/110758"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/110758","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Chimera: An efficient design space exploration tool for FPGA high-level synthesis","abstract":"In recent years, hardware accelerators based on field-programmable gate array (FPGA) started to be widely applied in large data centers, thanks to FPGA's extraordinary flexibility and power efficiency. However, with the high flexibility comes the difficulty in design and optimizations. Conventionally, the FPGA designs are written in low-level hardware descriptive languages, which means creating larger designs with complex behavior is extremely difficult. Therefore, high-level synthesis (HLS) tools have been created to close the gap between the design and compute capability. The HLS tools enable the user to create hardware designs using high-level languages and provide various optimization directives to help to improve the performance of the synthesized hardware. However, applying these optimizations to achieve high performance requires expert knowledge and abundant experience in HLS, which calls for an automated tuning tool to reduce the human efforts needed. In the light of this trend, we develop an efficient automated design space exploration (DSE) tool for applying HLS optimization directives, called Chimera. This tool can significantly reduce the human effort needed by automatically and efficiently exploring the design space of optimizations. Moreover, it is based on a multi-objective optimization method, which means that it can explore a Pareto curve consisting of design points that represent the best trade-offs between resource and latency. These points provide the designer with more choices that also facilitate system integration. In terms of efficiency, Chimera combines statistical learning, Bayesian optimization, and evolutionary algorithms to reduce the number of design points needed to be evaluated, such that the number of time-consuming HLS syntheses is minimized. In the experiments, it reaches the same or superior performance compared to highly optimized hand-tuned designs from the Rosetta benchmark suite.","abstract_html":"In recent years, hardware accelerators based on field-programmable gate array (FPGA) started to be widely applied in large data centers, thanks to FPGA's extraordinary flexibility and power efficiency. However, with the high flexibility comes the difficulty in design and optimizations. Conventionally, the FPGA designs are written in low-level hardware descriptive languages, which means creating larger designs with complex behavior is extremely difficult. Therefore, high-level synthesis (HLS) tools have been created to close the gap between the design and compute capability. The HLS tools enable the user to create hardware designs using high-level languages and provide various optimization directives to help to improve the performance of the synthesized hardware. However, applying these optimizations to achieve high performance requires expert knowledge and abundant experience in HLS, which calls for an automated tuning tool to reduce the human efforts needed. In the light of this trend, we develop an efficient automated design space exploration (DSE) tool for applying HLS optimization directives, called Chimera. This tool can significantly reduce the human effort needed by automatically and efficiently exploring the design space of optimizations. Moreover, it is based on a multi-objective optimization method, which means that it can explore a Pareto curve consisting of design points that represent the best trade-offs between resource and latency. These points provide the designer with more choices that also facilitate system integration. In terms of efficiency, Chimera combines statistical learning, Bayesian optimization, and evolutionary algorithms to reduce the number of design points needed to be evaluated, such that the number of time-consuming HLS syntheses is minimized. In the experiments, it reaches the same or superior performance compared to highly optimized hand-tuned designs from the Rosetta benchmark suite.","abstract_has_math":false,"creators":["Yu, Mang"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chen, Deming"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2021,"date_issued":"2021-09-17T02:34:51Z","date_published":"2021-09-17T02:34:51Z","updated_at":"2026-07-22T22:24:52Z","subjects":["FPGA","high-level synthesis","design space exploration"],"languages":["en"],"rights":["Copyright 2021 Mang Yu"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/110758","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chen, Deming"]},{"key":"dc:creator","label":"Author","values":["Yu, Mang"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2021-09-17T02:34:51Z","2023-09-17T02:34:57Z","2021-04-30","2021-05"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["FPGA","high-level synthesis","design space exploration"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2021 Mang Yu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/110758"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In recent years, hardware accelerators based on field-programmable gate array (FPGA) started to be widely applied in large data centers, thanks to FPGA's extraordinary flexibility and power efficiency. However, with the high flexibility comes the difficulty in design and optimizations. Conventionally, the FPGA designs are written in low-level hardware descriptive languages, which means creating larger designs with complex behavior is extremely difficult. Therefore, high-level synthesis (HLS) tools have been created to close the gap between the design and compute capability. The HLS tools enable the user to create hardware designs using high-level languages and provide various optimization directives to help to improve the performance of the synthesized hardware. However, applying these optimizations to achieve high performance requires expert knowledge and abundant experience in HLS, which calls for an automated tuning tool to reduce the human efforts needed. In the light of this trend, we develop an efficient automated design space exploration (DSE) tool for applying HLS optimization directives, called Chimera. This tool can significantly reduce the human effort needed by automatically and efficiently exploring the design space of optimizations. Moreover, it is based on a multi-objective optimization method, which means that it can explore a Pareto curve consisting of design points that represent the best trade-offs between resource and latency. These points provide the designer with more choices that also facilitate system integration. In terms of efficiency, Chimera combines statistical learning, Bayesian optimization, and evolutionary algorithms to reduce the number of design points needed to be evaluated, such that the number of time-consuming HLS syntheses is minimized. In the experiments, it reaches the same or superior performance compared to highly optimized hand-tuned designs from the Rosetta benchmark suite.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2023-05-01","The student, Mang Yu, accepted the attached license on 2021-04-30 at 11:46.","The student, Mang Yu, submitted this Thesis for approval on 2021-04-30 at 11:53.","This Thesis was approved for publication on 2021-04-30 at 13:31.","DSpace SAF Submission Ingestion Package generated from Vireo submission #16624 on 2021-09-16 at 17:06:58","Made available in DSpace on 2021-09-17T02:34:51Z (GMT). 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However, with the high flexibility comes the difficulty in design and optimizations. Conventionally, the FPGA designs are written in low-level hardware descriptive languages, which means creating larger designs with complex behavior is extremely difficult. Therefore, high-level synthesis (HLS) tools have been created to close the gap between the design and compute capability. The HLS tools enable the user to create hardware designs using high-level languages and provide various optimization directives to help to improve the performance of the synthesized hardware. However, applying these optimizations to achieve high performance requires expert knowledge and abundant experience in HLS, which calls for an automated tuning tool to reduce the human efforts needed. In the light of this trend, we develop an efficient automated design space exploration (DSE) tool for applying HLS optimization directives, called Chimera. This tool can significantly reduce the human effort needed by automatically and efficiently exploring the design space of optimizations. Moreover, it is based on a multi-objective optimization method, which means that it can explore a Pareto curve consisting of design points that represent the best trade-offs between resource and latency. These points provide the designer with more choices that also facilitate system integration. In terms of efficiency, Chimera combines statistical learning, Bayesian optimization, and evolutionary algorithms to reduce the number of design points needed to be evaluated, such that the number of time-consuming HLS syntheses is minimized. In the experiments, it reaches the same or superior performance compared to highly optimized hand-tuned designs from the Rosetta benchmark suite.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2023-05-01","The student, Mang Yu, accepted the attached license on 2021-04-30 at 11:46.","The student, Mang Yu, submitted this Thesis for approval on 2021-04-30 at 11:53.","This Thesis was approved for publication on 2021-04-30 at 13:31.","DSpace SAF Submission Ingestion Package generated from Vireo submission #16624 on 2021-09-16 at 17:06:58","Made available in DSpace on 2021-09-17T02:34:51Z (GMT). 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