{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/109333"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/109333","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Investigation of system-level ESD-induced failures","abstract":"Electrostatic discharge (ESD) is a phenomenon that can adversely impact the operation of systems. ESD is a short duration, high current stress which can cause the permanent failure of a system or temporary glitches in a system. Soft failures include any recoverable system malfunction, from resets to loss of stored data. They can be caused by noise entering signal pins or by supply voltage fluctuations. Soft failures have previously been studied by using test structures to identify failure mechanisms or actual products to identify the types of soft failures that occur. These models are either simplified or offer little to no insight into the cause of the soft failures. The first part of this dissertation addresses soft failures within a fully functional semi-custom microcontroller. This allows for both an understanding into the exact causes of soft failures as well as testing for effects of soft failures from ESD on operating software. The second part of this work focuses on latch-up in reverse body biased core circuitry. Latch-up is a phenomenon where parasitic devices within a CMOS structure turn on and stay on, shunting current from power to ground, often causing permanent failure. Latch-up has often been looked at from a substrate current injection point of view, however, measurement of a reverse body biased chip shows that latch-up can occur due to supply bounce. An analytic model and SPICE simulation verify the phenomenon, and with the help of simulation, methods of increasing robustness are discussed.","abstract_html":"Electrostatic discharge (ESD) is a phenomenon that can adversely impact the operation of systems. ESD is a short duration, high current stress which can cause the permanent failure of a system or temporary glitches in a system. Soft failures include any recoverable system malfunction, from resets to loss of stored data. They can be caused by noise entering signal pins or by supply voltage fluctuations. Soft failures have previously been studied by using test structures to identify failure mechanisms or actual products to identify the types of soft failures that occur. These models are either simplified or offer little to no insight into the cause of the soft failures. The first part of this dissertation addresses soft failures within a fully functional semi-custom microcontroller. This allows for both an understanding into the exact causes of soft failures as well as testing for effects of soft failures from ESD on operating software. The second part of this work focuses on latch-up in reverse body biased core circuitry. Latch-up is a phenomenon where parasitic devices within a CMOS structure turn on and stay on, shunting current from power to ground, often causing permanent failure. Latch-up has often been looked at from a substrate current injection point of view, however, measurement of a reverse body biased chip shows that latch-up can occur due to supply bounce. An analytic model and SPICE simulation verify the phenomenon, and with the help of simulation, methods of increasing robustness are discussed.","abstract_has_math":false,"creators":["Vora, Sandeep Gautam"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse","Hanumolu, Pavan","Zhou, Jin","Schutt-Ainé, José"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2021,"date_issued":"2021-03-05T21:36:47Z","date_published":"2021-03-05T21:36:47Z","updated_at":"2026-07-22T22:24:50Z","subjects":["Electrostatic Discharge","ESD","IC","Reliability","EM simulation"],"languages":["en"],"rights":["Copyright 2020 Sandeep Vora"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/109333","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse","Hanumolu, Pavan","Zhou, Jin","Schutt-Ainé, José"]},{"key":"dc:creator","label":"Author","values":["Vora, Sandeep Gautam"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2021-03-05T21:36:47Z","2020-09-04","2020-12"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrostatic Discharge","ESD","IC","Reliability","EM simulation"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2020 Sandeep Vora"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/109333"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Electrostatic discharge (ESD) is a phenomenon that can adversely impact the operation of systems. ESD is a short duration, high current stress which can cause the permanent failure of a system or temporary glitches in a system. Soft failures include any recoverable system malfunction, from resets to loss of stored data. They can be caused by noise entering signal pins or by supply voltage fluctuations. Soft failures have previously been studied by using test structures to identify failure mechanisms or actual products to identify the types of soft failures that occur. These models are either simplified or offer little to no insight into the cause of the soft failures. The first part of this dissertation addresses soft failures within a fully functional semi-custom microcontroller. This allows for both an understanding into the exact causes of soft failures as well as testing for effects of soft failures from ESD on operating software. The second part of this work focuses on latch-up in reverse body biased core circuitry. Latch-up is a phenomenon where parasitic devices within a CMOS structure turn on and stay on, shunting current from power to ground, often causing permanent failure. Latch-up has often been looked at from a substrate current injection point of view, however, measurement of a reverse body biased chip shows that latch-up can occur due to supply bounce. An analytic model and SPICE simulation verify the phenomenon, and with the help of simulation, methods of increasing robustness are discussed.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2021-03-04 without embargo terms","The student, Sandeep Vora, accepted the attached license on 2020-09-03 at 11:19.","The student, Sandeep Vora, submitted this Dissertation for approval on 2020-09-03 at 11:26.","This Dissertation was approved for publication on 2020-09-04 at 08:33.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15797 on 2021-03-04 at 15:33:43","Made available in DSpace on 2021-03-05T21:36:47Z (GMT). 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Soft failures include any recoverable system malfunction, from resets to loss of stored data. They can be caused by noise entering signal pins or by supply voltage fluctuations. Soft failures have previously been studied by using test structures to identify failure mechanisms or actual products to identify the types of soft failures that occur. These models are either simplified or offer little to no insight into the cause of the soft failures. The first part of this dissertation addresses soft failures within a fully functional semi-custom microcontroller. This allows for both an understanding into the exact causes of soft failures as well as testing for effects of soft failures from ESD on operating software. The second part of this work focuses on latch-up in reverse body biased core circuitry. Latch-up is a phenomenon where parasitic devices within a CMOS structure turn on and stay on, shunting current from power to ground, often causing permanent failure. Latch-up has often been looked at from a substrate current injection point of view, however, measurement of a reverse body biased chip shows that latch-up can occur due to supply bounce. An analytic model and SPICE simulation verify the phenomenon, and with the help of simulation, methods of increasing robustness are discussed.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2021-03-04 without embargo terms","The student, Sandeep Vora, accepted the attached license on 2020-09-03 at 11:19.","The student, Sandeep Vora, submitted this Dissertation for approval on 2020-09-03 at 11:26.","This Dissertation was approved for publication on 2020-09-04 at 08:33.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15797 on 2021-03-04 at 15:33:43","Made available in DSpace on 2021-03-05T21:36:47Z (GMT). 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