{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/109322"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/109322","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Extending secure and trusted computation to FPGA accelerators","abstract":"As the demand for computation power grows rapidly, the need for security and privacy has become stronger in cloud computing and heterogeneous systems. Several cloud and data centers have already started deploying Field Programmable Gate Arrays (FPGAs) as reconfigurable accelerators with high performance and energy efficiency. However, the current infrastructure design provides little or no support for security in external accelerators. Existing trusted computing solutions such as Intel SGX or ARM TrustZone target at CPU-only environments, making external accelerators and peripheral devices unprotected. This work proposes a new scheme to extend trust computing for FPGA accelerators. The scheme consists of a security manager (SM) with hardware root of trust through standard cryptographic primitives and remote attestation of the SM as well as the custom accelerators. Our prototype implementation of the FPGA enclave framework minimized the performance overhead (due to the security features) compared to a state-of-the-art CPU-based enclave framework, Intel SGX, while enjoying the benefit of improved performance through hardware acceleration. From our evaluation results, an accelerated histogram application running in our FPGA enclave environment achieved a 6.2x performance speedup on average compared to the same application running inside an Intel SGX enclave.","abstract_html":"As the demand for computation power grows rapidly, the need for security and privacy has become stronger in cloud computing and heterogeneous systems. Several cloud and data centers have already started deploying Field Programmable Gate Arrays (FPGAs) as reconfigurable accelerators with high performance and energy efficiency. However, the current infrastructure design provides little or no support for security in external accelerators. Existing trusted computing solutions such as Intel SGX or ARM TrustZone target at CPU-only environments, making external accelerators and peripheral devices unprotected. This work proposes a new scheme to extend trust computing for FPGA accelerators. The scheme consists of a security manager (SM) with hardware root of trust through standard cryptographic primitives and remote attestation of the SM as well as the custom accelerators. Our prototype implementation of the FPGA enclave framework minimized the performance overhead (due to the security features) compared to a state-of-the-art CPU-based enclave framework, Intel SGX, while enjoying the benefit of improved performance through hardware acceleration. From our evaluation results, an accelerated histogram application running in our FPGA enclave environment achieved a 6.2x performance speedup on average compared to the same application running inside an Intel SGX enclave.","abstract_has_math":false,"creators":["Ren, Wei"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chen, Deming"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2021,"date_issued":"2021-03-05T21:33:16Z","date_published":"2021-03-05T21:33:16Z","updated_at":"2026-07-22T22:24:50Z","subjects":["Security","Trusted Computation","FPGA"],"languages":["en"],"rights":["Copyright 2020 Wei Ren"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/109322","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chen, Deming"]},{"key":"dc:creator","label":"Author","values":["Ren, Wei"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2021-03-05T21:33:16Z","2020-08-17","2020-12"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Security","Trusted Computation","FPGA"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2020 Wei Ren"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/109322"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["As the demand for computation power grows rapidly, the need for security and privacy has become stronger in cloud computing and heterogeneous systems. Several cloud and data centers have already started deploying Field Programmable Gate Arrays (FPGAs) as reconfigurable accelerators with high performance and energy efficiency. However, the current infrastructure design provides little or no support for security in external accelerators. Existing trusted computing solutions such as Intel SGX or ARM TrustZone target at CPU-only environments, making external accelerators and peripheral devices unprotected. This work proposes a new scheme to extend trust computing for FPGA accelerators. The scheme consists of a security manager (SM) with hardware root of trust through standard cryptographic primitives and remote attestation of the SM as well as the custom accelerators. Our prototype implementation of the FPGA enclave framework minimized the performance overhead (due to the security features) compared to a state-of-the-art CPU-based enclave framework, Intel SGX, while enjoying the benefit of improved performance through hardware acceleration. From our evaluation results, an accelerated histogram application running in our FPGA enclave environment achieved a 6.2x performance speedup on average compared to the same application running inside an Intel SGX enclave.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2021-03-04 without embargo terms","The student, Wei Ren, accepted the attached license on 2020-08-15 at 10:25.","The student, Wei Ren, submitted this Thesis for approval on 2020-08-15 at 10:39.","This Thesis was approved for publication on 2020-08-17 at 10:58.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15773 on 2021-03-04 at 15:33:24","Made available in DSpace on 2021-03-05T21:33:16Z (GMT). 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Existing trusted computing solutions such as Intel SGX or ARM TrustZone target at CPU-only environments, making external accelerators and peripheral devices unprotected. This work proposes a new scheme to extend trust computing for FPGA accelerators. The scheme consists of a security manager (SM) with hardware root of trust through standard cryptographic primitives and remote attestation of the SM as well as the custom accelerators. Our prototype implementation of the FPGA enclave framework minimized the performance overhead (due to the security features) compared to a state-of-the-art CPU-based enclave framework, Intel SGX, while enjoying the benefit of improved performance through hardware acceleration. From our evaluation results, an accelerated histogram application running in our FPGA enclave environment achieved a 6.2x performance speedup on average compared to the same application running inside an Intel SGX enclave.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2021-03-04 without embargo terms","The student, Wei Ren, accepted the attached license on 2020-08-15 at 10:25.","The student, Wei Ren, submitted this Thesis for approval on 2020-08-15 at 10:39.","This Thesis was approved for publication on 2020-08-17 at 10:58.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15773 on 2021-03-04 at 15:33:24","Made available in DSpace on 2021-03-05T21:33:16Z (GMT). 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