{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/108669"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/108669","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Clock distribution network techniques","abstract":"Clock distribution networks are essential to synchronous systems. The design of these networks affects the system performance dramatically and sometimes determines whether the chip can function properly or not. This thesis first describes in detail how a synchronous system works. Based on the design metrics such as the clock skew requirement and power requirement, different clock distribution network topologies are then presented, including the popular H tree, grid and serpentine structures. Finally, commonly used techniques for improving clock skew, jitter and power are discussed and conclusions are offered.","abstract_html":"Clock distribution networks are essential to synchronous systems. The design of these networks affects the system performance dramatically and sometimes determines whether the chip can function properly or not. This thesis first describes in detail how a synchronous system works. Based on the design metrics such as the clock skew requirement and power requirement, different clock distribution network topologies are then presented, including the popular H tree, grid and serpentine structures. Finally, commonly used techniques for improving clock skew, jitter and power are discussed and conclusions are offered.","abstract_has_math":false,"creators":["Chen, Shuang"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hanumolu, Pavan Kumar"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2020,"date_issued":"2020-10-07T22:48:09Z","date_published":"2020-10-07T22:48:09Z","updated_at":"2026-07-22T22:24:48Z","subjects":["clock distribution network","synchronous system"],"languages":["en"],"rights":["Copyright 2020 Shuang Chen"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/108669","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hanumolu, Pavan Kumar"]},{"key":"dc:creator","label":"Author","values":["Chen, Shuang"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2020-10-07T22:48:09Z","2022-10-07T22:50:13Z","2020-06-29","2020-08"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["clock distribution network","synchronous system"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2020 Shuang Chen"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/108669"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Clock distribution networks are essential to synchronous systems. The design of these networks affects the system performance dramatically and sometimes determines whether the chip can function properly or not. This thesis first describes in detail how a synchronous system works. Based on the design metrics such as the clock skew requirement and power requirement, different clock distribution network topologies are then presented, including the popular H tree, grid and serpentine structures. Finally, commonly used techniques for improving clock skew, jitter and power are discussed and conclusions are offered.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2022-08-01","The student, Shuang Chen, accepted the attached license on 2020-06-26 at 16:40.","The student, Shuang Chen, submitted this Thesis for approval on 2020-06-26 at 16:50.","This Thesis was approved for publication on 2020-06-29 at 15:08.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15473 on 2020-10-02 at 15:49:41","Made available in DSpace on 2020-10-07T22:48:09Z (GMT). No. of bitstreams: 2 CHEN-THESIS-2020.pdf: 770570 bytes, checksum: 068cedd8d6fc58470b4144a4e4835913 (MD5) LICENSE.txt: 4208 bytes, checksum: 65a24e6badad337f0b898ca1b859ce1f (MD5) Previous issue date: 2020-06-29","Embargo set by: Seth Robbins for item 116297 Lift date: 2022-10-07T22:48:14Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 116297 Lift date: 2022-10-07T22:50:13Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Author requested closed access (OA after 2yrs) in Vireo ETD system","Limited"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Clock distribution network techniques"]}]}],"canonical_facts":{"dc:contributor":["Hanumolu, Pavan Kumar"],"dc:creator":["Chen, Shuang"],"dc:date":["2020-10-07T22:48:09Z","2022-10-07T22:50:13Z","2020-06-29","2020-08"],"dc:description":["Clock distribution networks are essential to synchronous systems. The design of these networks affects the system performance dramatically and sometimes determines whether the chip can function properly or not. This thesis first describes in detail how a synchronous system works. Based on the design metrics such as the clock skew requirement and power requirement, different clock distribution network topologies are then presented, including the popular H tree, grid and serpentine structures. Finally, commonly used techniques for improving clock skew, jitter and power are discussed and conclusions are offered.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2022-08-01","The student, Shuang Chen, accepted the attached license on 2020-06-26 at 16:40.","The student, Shuang Chen, submitted this Thesis for approval on 2020-06-26 at 16:50.","This Thesis was approved for publication on 2020-06-29 at 15:08.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15473 on 2020-10-02 at 15:49:41","Made available in DSpace on 2020-10-07T22:48:09Z (GMT). No. of bitstreams: 2 CHEN-THESIS-2020.pdf: 770570 bytes, checksum: 068cedd8d6fc58470b4144a4e4835913 (MD5) LICENSE.txt: 4208 bytes, checksum: 65a24e6badad337f0b898ca1b859ce1f (MD5) Previous issue date: 2020-06-29","Embargo set by: Seth Robbins for item 116297 Lift date: 2022-10-07T22:48:14Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 116297 Lift date: 2022-10-07T22:50:13Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Author requested closed access (OA after 2yrs) in Vireo ETD system","Limited"],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/108669"],"dc:language":["en"],"dc:rights":["Copyright 2020 Shuang Chen"],"dc:subject":["clock distribution network","synchronous system"],"dc:title":["Clock distribution network techniques"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:48Z"}