{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/108103"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/108103","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"High-performance reference frequency generation techniques","abstract":"Low-noise high-frequency fast-startup reference frequency generators are needed in high-performance power-efficient communication systems. Frequency synthesizers that generate high-frequency clocks in modern wireline/wireless transceivers require high-frequency reference clocks to achieve excellent noise performance. In the first part of this work, we present ways to generate such reference clocks at 4 times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216MHz reference clock with an integrated jitter of 77fsrms is generated from a 54MHz Pierce XO. A ring oscillator based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65nm CMOS process, the proposed clock multiplier occupies an active area of 0.16mm2 and achieves 366fsrms integrated jitter at 4.752GHz output frequency while consuming 6.5mW power from a 1.0V supply of which 1.5mW is consumed in the quadrupler. Heavily duty-cycled communication systems that implement aggressive dynamic power management schemes to reduce average power consumption require fast-startup reference clocks which demand fast-startup crystal oscillators. In the second part of this thesis, we present ways to improve the startup time of crystal oscillators. Using a two-step injection technique in a three-step process, the proposed technique reduces the crystal oscillator startup time to within 1.5x the theoretical minimum. By solving the differential equation governing a crystal resonator under injection for arbitrary injection frequency, the behavior of energy buildup inside a crystal resonator is analyzed and used to determine optimum injection time as a function of the desired crystal oscillator steady-state amplitude and injection frequency error. Bounds on tolerable injection frequency error to guarantee the existence of optimal timing are provided. Fabricated in a 65nm CMOS process, the proposed 54MHz fast-startup crystal oscillator occupies an active area of 0.075mm2 and achieves a startup time of less than 20us across a temperature range of -40oC to 85oC while consuming a startup energy of 34.9nJ and operating from a 1.0V supply.","abstract_html":"Low-noise high-frequency fast-startup reference frequency generators are needed in high-performance power-efficient communication systems. Frequency synthesizers that generate high-frequency clocks in modern wireline/wireless transceivers require high-frequency reference clocks to achieve excellent noise performance. In the first part of this work, we present ways to generate such reference clocks at 4 times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216MHz reference clock with an integrated jitter of 77fsrms is generated from a 54MHz Pierce XO. A ring oscillator based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65nm CMOS process, the proposed clock multiplier occupies an active area of 0.16mm2 and achieves 366fsrms integrated jitter at 4.752GHz output frequency while consuming 6.5mW power from a 1.0V supply of which 1.5mW is consumed in the quadrupler. Heavily duty-cycled communication systems that implement aggressive dynamic power management schemes to reduce average power consumption require fast-startup reference clocks which demand fast-startup crystal oscillators. In the second part of this thesis, we present ways to improve the startup time of crystal oscillators. Using a two-step injection technique in a three-step process, the proposed technique reduces the crystal oscillator startup time to within 1.5x the theoretical minimum. By solving the differential equation governing a crystal resonator under injection for arbitrary injection frequency, the behavior of energy buildup inside a crystal resonator is analyzed and used to determine optimum injection time as a function of the desired crystal oscillator steady-state amplitude and injection frequency error. Bounds on tolerable injection frequency error to guarantee the existence of optimal timing are provided. Fabricated in a 65nm CMOS process, the proposed 54MHz fast-startup crystal oscillator occupies an active area of 0.075mm2 and achieves a startup time of less than 20us across a temperature range of -40oC to 85oC while consuming a startup energy of 34.9nJ and operating from a 1.0V supply.","abstract_has_math":false,"creators":["Megawer, Karim M."],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hanumolu, Pavan K","Shanbhag, Naresh R","Schutt-Aine, Jose E","Zhou, Jin"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2020,"date_issued":"2020-08-26T23:51:27Z","date_published":"2020-08-26T23:51:27Z","updated_at":"2026-07-22T22:24:47Z","subjects":["Crystal oscillator (XO)","digitally controlled oscillator (DCO)","duty-cycle correction","frequency quadrupler","injection-locked clock multiplier (ILCM)","jitter","least mean square (LMS)","ring oscillator (RO)","startup time"],"languages":["en"],"rights":["Copyright 2020 Karim M. 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A ring oscillator based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65nm CMOS process, the proposed clock multiplier occupies an active area of 0.16mm2 and achieves 366fsrms integrated jitter at 4.752GHz output frequency while consuming 6.5mW power from a 1.0V supply of which 1.5mW is consumed in the quadrupler. Heavily duty-cycled communication systems that implement aggressive dynamic power management schemes to reduce average power consumption require fast-startup reference clocks which demand fast-startup crystal oscillators. In the second part of this thesis, we present ways to improve the startup time of crystal oscillators. Using a two-step injection technique in a three-step process, the proposed technique reduces the crystal oscillator startup time to within 1.5x the theoretical minimum. By solving the differential equation governing a crystal resonator under injection for arbitrary injection frequency, the behavior of energy buildup inside a crystal resonator is analyzed and used to determine optimum injection time as a function of the desired crystal oscillator steady-state amplitude and injection frequency error. Bounds on tolerable injection frequency error to guarantee the existence of optimal timing are provided. Fabricated in a 65nm CMOS process, the proposed 54MHz fast-startup crystal oscillator occupies an active area of 0.075mm2 and achieves a startup time of less than 20us across a temperature range of -40oC to 85oC while consuming a startup energy of 34.9nJ and operating from a 1.0V supply.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2022-05-01","The student, Karim Megawer, accepted the attached license on 2020-04-10 at 14:11.","The student, Karim Megawer, submitted this Dissertation for approval on 2020-04-10 at 14:35.","This Dissertation was approved for publication on 2020-04-13 at 10:25.","DSpace SAF Submission Ingestion Package generated from Vireo submission #14955 on 2020-08-25 at 17:27:15","Made available in DSpace on 2020-08-26T23:51:27Z (GMT). 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Frequency synthesizers that generate high-frequency clocks in modern wireline/wireless transceivers require high-frequency reference clocks to achieve excellent noise performance. In the first part of this work, we present ways to generate such reference clocks at 4 times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216MHz reference clock with an integrated jitter of 77fsrms is generated from a 54MHz Pierce XO. A ring oscillator based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65nm CMOS process, the proposed clock multiplier occupies an active area of 0.16mm2 and achieves 366fsrms integrated jitter at 4.752GHz output frequency while consuming 6.5mW power from a 1.0V supply of which 1.5mW is consumed in the quadrupler. Heavily duty-cycled communication systems that implement aggressive dynamic power management schemes to reduce average power consumption require fast-startup reference clocks which demand fast-startup crystal oscillators. In the second part of this thesis, we present ways to improve the startup time of crystal oscillators. Using a two-step injection technique in a three-step process, the proposed technique reduces the crystal oscillator startup time to within 1.5x the theoretical minimum. By solving the differential equation governing a crystal resonator under injection for arbitrary injection frequency, the behavior of energy buildup inside a crystal resonator is analyzed and used to determine optimum injection time as a function of the desired crystal oscillator steady-state amplitude and injection frequency error. Bounds on tolerable injection frequency error to guarantee the existence of optimal timing are provided. Fabricated in a 65nm CMOS process, the proposed 54MHz fast-startup crystal oscillator occupies an active area of 0.075mm2 and achieves a startup time of less than 20us across a temperature range of -40oC to 85oC while consuming a startup energy of 34.9nJ and operating from a 1.0V supply.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2022-05-01","The student, Karim Megawer, accepted the attached license on 2020-04-10 at 14:11.","The student, Karim Megawer, submitted this Dissertation for approval on 2020-04-10 at 14:35.","This Dissertation was approved for publication on 2020-04-13 at 10:25.","DSpace SAF Submission Ingestion Package generated from Vireo submission #14955 on 2020-08-25 at 17:27:15","Made available in DSpace on 2020-08-26T23:51:27Z (GMT). No. of bitstreams: 7 MEGAWER-DISSERTATION-2020.pdf: 5390393 bytes, checksum: 1d2d82abda73df10b3c928895b399382 (MD5) ISSCC 2018.pdf: 130062 bytes, checksum: 142ad5133aca98266f5802f840ac9ce8 (MD5) ISSCC 2019.pdf: 130604 bytes, checksum: 73d187b72c3e5229f55026164e813c04 (MD5) JSSC 2018.pdf: 129165 bytes, checksum: ac80e32401550f4173d2dee888ea4bad (MD5) JSSC 2019.pdf: 128731 bytes, checksum: c1ffb11f932f76ff29c72ac4afdf0a96 (MD5) LICENSE.txt: 4210 bytes, checksum: 2245877475f79267be8db9059c516f43 (MD5) PROQUEST_LICENSE.txt: 4556 bytes, checksum: b1469d9a726b807b388c722fac227043 (MD5) Previous issue date: 2020-04-13","Embargo set by: Seth Robbins for item 115712 Lift date: 2022-08-26T23:51:32Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 115712 Lift date: 2022-08-26T23:54:40Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 115712 Lift date: 2022-08-26T23:55:59Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 115712 Lift date: 2022-08-26T23:57:28Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 115712 Lift date: 2022-08-26T23:58:55Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only"],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/108103"],"dc:language":["en"],"dc:rights":["Copyright 2020 Karim M. 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