{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/108033"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/108033","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"ESD circuit design and measurement techniques","abstract":"Part 1 of this thesis presents a method to measure sub-nanosecond reverse recovery in wafer-level test structures. The setup uses a transmission line pulse generator with a time domain through connection to measure the device under test current. The setup is then used to measure reverse recovery in a 65 nm CMOS ESD diode, and it is found that a quasi-static compact model does not accurately describe the observed transient. A non-quasi-static charge control model is used to accurately simulate both the reverse recovery and forward bias behavior. Part 2 of this thesis reports the design and fabrication of an active feedback based high-voltage tolerant power clamp with optimally biased positive and negative feedback to bypass the trade-off between ESD performance and mis-trigger immunity. The circuit was fabricated in 28 nm CMOS, and characterization results show a 70% improvement in failure current over previous designs while maintaining mis-trigger immunity.","abstract_html":"Part 1 of this thesis presents a method to measure sub-nanosecond reverse recovery in wafer-level test structures. The setup uses a transmission line pulse generator with a time domain through connection to measure the device under test current. The setup is then used to measure reverse recovery in a 65 nm CMOS ESD diode, and it is found that a quasi-static compact model does not accurately describe the observed transient. A non-quasi-static charge control model is used to accurately simulate both the reverse recovery and forward bias behavior. Part 2 of this thesis reports the design and fabrication of an active feedback based high-voltage tolerant power clamp with optimally biased positive and negative feedback to bypass the trade-off between ESD performance and mis-trigger immunity. The circuit was fabricated in 28 nm CMOS, and characterization results show a 70% improvement in failure current over previous designs while maintaining mis-trigger immunity.","abstract_has_math":false,"creators":["Ayling, Alex Eben"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2020,"date_issued":"2020-08-26T21:58:01Z","date_published":"2020-08-26T21:58:01Z","updated_at":"2026-07-22T22:24:47Z","subjects":["Electrostatic Discharge, Integrated Circuits"],"languages":["en"],"rights":["Copyright 2020 Alex Ayling"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/108033","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse"]},{"key":"dc:creator","label":"Author","values":["Ayling, Alex Eben"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2020-08-26T21:58:01Z","2020-05-12","2020-05"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrostatic Discharge, Integrated Circuits"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2020 Alex Ayling"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/108033"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Part 1 of this thesis presents a method to measure sub-nanosecond reverse recovery in wafer-level test structures. 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A non-quasi-static charge control model is used to accurately simulate both the reverse recovery and forward bias behavior. Part 2 of this thesis reports the design and fabrication of an active feedback based high-voltage tolerant power clamp with optimally biased positive and negative feedback to bypass the trade-off between ESD performance and mis-trigger immunity. The circuit was fabricated in 28 nm CMOS, and characterization results show a 70% improvement in failure current over previous designs while maintaining mis-trigger immunity.","Submission original under an indefinite embargo labeled 'Open Access'. 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