{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/108002"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/108002","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Memory access patterns and page promotion in hybrid memory systems","abstract":"Hybrid heterogeneous memory systems are becoming increasingly popular as traditional memory systems are hitting performance and energy walls in processing data-intensive applications, which are becoming the norm with the resurgence of machine learning, big data, graph analytics, and database management systems, especially in modern datacenters. In addition to the massive data that these applications process, they exhibit varying and non-deterministic memory access patterns making I/O latency a prime criterion in the design considerations that go into building modern computing systems to support them. A traditional memory system moves data by swapping pages between the faster DRAM and the slower SSD. While applications with sequential accesses have better traffic between the DRAM and the SSD, applications with random page accesses, such as large graphs, often produce high traffic and exhibit little or no reuse of pages swapped into the DRAM. This thesis proposes a technique to identify memory access patterns, and a scalable and distributed technique to determine when pages should be promoted from the slower memory system to the faster memory system, thereby reducing I/O traffic. The proposed page promotion design shows up to 6.74x reduction in page traffic and 1.21x increase in the total hit rate of a data-intensive application with uniformly distributed random memory accesses.","abstract_html":"Hybrid heterogeneous memory systems are becoming increasingly popular as traditional memory systems are hitting performance and energy walls in processing data-intensive applications, which are becoming the norm with the resurgence of machine learning, big data, graph analytics, and database management systems, especially in modern datacenters. In addition to the massive data that these applications process, they exhibit varying and non-deterministic memory access patterns making I/O latency a prime criterion in the design considerations that go into building modern computing systems to support them. A traditional memory system moves data by swapping pages between the faster DRAM and the slower SSD. While applications with sequential accesses have better traffic between the DRAM and the SSD, applications with random page accesses, such as large graphs, often produce high traffic and exhibit little or no reuse of pages swapped into the DRAM. This thesis proposes a technique to identify memory access patterns, and a scalable and distributed technique to determine when pages should be promoted from the slower memory system to the faster memory system, thereby reducing I/O traffic. The proposed page promotion design shows up to 6.74x reduction in page traffic and 1.21x increase in the total hit rate of a data-intensive application with uniformly distributed random memory accesses.","abstract_has_math":false,"creators":["Agarwal, Ayush"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hwu, Wen-mei W"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2020,"date_issued":"2020-08-26T21:54:56Z","date_published":"2020-08-26T21:54:56Z","updated_at":"2026-07-22T22:24:47Z","subjects":["memory system","data-intensive","prefetching","hybrid memory system","page promotion","page migration"],"languages":["en"],"rights":["Copyright 2020 Ayush Agarwal"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/108002","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hwu, Wen-mei W"]},{"key":"dc:creator","label":"Author","values":["Agarwal, Ayush"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2020-08-26T21:54:56Z","2020-05-10","2020-05"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["memory system","data-intensive","prefetching","hybrid memory system","page promotion","page migration"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2020 Ayush Agarwal"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/108002"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Hybrid heterogeneous memory systems are becoming increasingly popular as traditional memory systems are hitting performance and energy walls in processing data-intensive applications, which are becoming the norm with the resurgence of machine learning, big data, graph analytics, and database management systems, especially in modern datacenters. In addition to the massive data that these applications process, they exhibit varying and non-deterministic memory access patterns making I/O latency a prime criterion in the design considerations that go into building modern computing systems to support them. A traditional memory system moves data by swapping pages between the faster DRAM and the slower SSD. While applications with sequential accesses have better traffic between the DRAM and the SSD, applications with random page accesses, such as large graphs, often produce high traffic and exhibit little or no reuse of pages swapped into the DRAM. This thesis proposes a technique to identify memory access patterns, and a scalable and distributed technique to determine when pages should be promoted from the slower memory system to the faster memory system, thereby reducing I/O traffic. The proposed page promotion design shows up to 6.74x reduction in page traffic and 1.21x increase in the total hit rate of a data-intensive application with uniformly distributed random memory accesses.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2020-08-25 without embargo terms","The student, Ayush Agarwal, accepted the attached license on 2020-05-06 at 09:23.","The student, Ayush Agarwal, submitted this Thesis for approval on 2020-05-06 at 09:34.","This Thesis was approved for publication on 2020-05-10 at 16:18.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15242 on 2020-08-25 at 17:12:34","Made available in DSpace on 2020-08-26T21:54:56Z (GMT). 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In addition to the massive data that these applications process, they exhibit varying and non-deterministic memory access patterns making I/O latency a prime criterion in the design considerations that go into building modern computing systems to support them. A traditional memory system moves data by swapping pages between the faster DRAM and the slower SSD. While applications with sequential accesses have better traffic between the DRAM and the SSD, applications with random page accesses, such as large graphs, often produce high traffic and exhibit little or no reuse of pages swapped into the DRAM. This thesis proposes a technique to identify memory access patterns, and a scalable and distributed technique to determine when pages should be promoted from the slower memory system to the faster memory system, thereby reducing I/O traffic. The proposed page promotion design shows up to 6.74x reduction in page traffic and 1.21x increase in the total hit rate of a data-intensive application with uniformly distributed random memory accesses.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2020-08-25 without embargo terms","The student, Ayush Agarwal, accepted the attached license on 2020-05-06 at 09:23.","The student, Ayush Agarwal, submitted this Thesis for approval on 2020-05-06 at 09:34.","This Thesis was approved for publication on 2020-05-10 at 16:18.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15242 on 2020-08-25 at 17:12:34","Made available in DSpace on 2020-08-26T21:54:56Z (GMT). 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