{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/104949"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/104949","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Open-source high-level synthesis of tensorflow dataflow graphs using LegUp","abstract":"A flow is presented for synthesizing Tensorflow computation graphs into FPGA accelerators using the open-source high-level synthesis (HLS) tool LegUp. The Tensorflow computation graph is represented translated from an intermediate representation in Tensorflow's Accelerated Linear Algebra (XLA) compiler called High Level Optimizer (HLO). This is translated into LLVM intermediate representation (IR) using a modified version of XLA's CPU backend. These modifications enable users to leverage IP modules for computation-intensive operations. For a simple instance of matrix multiply, using even a naively implemented IP is shown to give a 1.7x speedup over baseline accelerators synthesized from the original CPU backend.","abstract_html":"A flow is presented for synthesizing Tensorflow computation graphs into FPGA accelerators using the open-source high-level synthesis (HLS) tool LegUp. The Tensorflow computation graph is represented translated from an intermediate representation in Tensorflow's Accelerated Linear Algebra (XLA) compiler called High Level Optimizer (HLO). This is translated into LLVM intermediate representation (IR) using a modified version of XLA's CPU backend. These modifications enable users to leverage IP modules for computation-intensive operations. For a simple instance of matrix multiply, using even a naively implemented IP is shown to give a 1.7x speedup over baseline accelerators synthesized from the original CPU backend.","abstract_has_math":false,"creators":["Umenthum, Kenneth Richard"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chen, Deming"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2019,"date_issued":"2019-08-23T20:05:25Z","date_published":"2019-08-23T20:05:25Z","updated_at":"2026-07-22T22:24:44Z","subjects":["tensorflow","legup","high level synthesis","machine learning"],"languages":["en"],"rights":["Copyright 2019 Kenneth Richard Umenthum"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/104949","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chen, Deming"]},{"key":"dc:creator","label":"Author","values":["Umenthum, Kenneth Richard"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2019-08-23T20:05:25Z","2019-04-26","2019-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["tensorflow","legup","high level synthesis","machine learning"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2019 Kenneth Richard Umenthum"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/104949"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["A flow is presented for synthesizing Tensorflow computation graphs into FPGA accelerators using the open-source high-level synthesis (HLS) tool LegUp. The Tensorflow computation graph is represented translated from an intermediate representation in Tensorflow's Accelerated Linear Algebra (XLA) compiler called High Level Optimizer (HLO). This is translated into LLVM intermediate representation (IR) using a modified version of XLA's CPU backend. These modifications enable users to leverage IP modules for computation-intensive operations. For a simple instance of matrix multiply, using even a naively implemented IP is shown to give a 1.7x speedup over baseline accelerators synthesized from the original CPU backend.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2019-08-22 without embargo terms","The student, Kenneth Umenthum, accepted the attached license on 2019-04-26 at 11:16.","The student, Kenneth Umenthum, submitted this Thesis for approval on 2019-04-26 at 11:23.","This Thesis was approved for publication on 2019-04-26 at 11:43.","DSpace SAF Submission Ingestion Package generated from Vireo submission #13944 on 2019-08-22 at 14:47:09","Made available in DSpace on 2019-08-23T20:05:25Z (GMT). No. of bitstreams: 2 UMENTHUM-THESIS-2019.pdf: 315718 bytes, checksum: 0ac572af333411234596f7d2727c6bce (MD5) LICENSE.txt: 4213 bytes, checksum: 3b8d5c692ea83afe0360b62655d00e16 (MD5) Previous issue date: 2019-04-26"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Open-source high-level synthesis of tensorflow dataflow graphs using LegUp"]}]}],"canonical_facts":{"dc:contributor":["Chen, Deming"],"dc:creator":["Umenthum, Kenneth Richard"],"dc:date":["2019-08-23T20:05:25Z","2019-04-26","2019-05"],"dc:description":["A flow is presented for synthesizing Tensorflow computation graphs into FPGA accelerators using the open-source high-level synthesis (HLS) tool LegUp. The Tensorflow computation graph is represented translated from an intermediate representation in Tensorflow's Accelerated Linear Algebra (XLA) compiler called High Level Optimizer (HLO). This is translated into LLVM intermediate representation (IR) using a modified version of XLA's CPU backend. These modifications enable users to leverage IP modules for computation-intensive operations. For a simple instance of matrix multiply, using even a naively implemented IP is shown to give a 1.7x speedup over baseline accelerators synthesized from the original CPU backend.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2019-08-22 without embargo terms","The student, Kenneth Umenthum, accepted the attached license on 2019-04-26 at 11:16.","The student, Kenneth Umenthum, submitted this Thesis for approval on 2019-04-26 at 11:23.","This Thesis was approved for publication on 2019-04-26 at 11:43.","DSpace SAF Submission Ingestion Package generated from Vireo submission #13944 on 2019-08-22 at 14:47:09","Made available in DSpace on 2019-08-23T20:05:25Z (GMT). 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