{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/102841"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/102841","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Tutorial on direct digital synthesizer structure improvements and static timing analysis","abstract":"The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have been rapidly developed. Because of FPGAs’ high speed, high integration and field-programmable advantages, the devices are widely used in digital processing and are increasingly favored by hardware circuit design engineers. FPGAs also provide a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such high-speed switching, fine tunability and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate some ways to optimize the DDS structure to save hardware resources and increase chip speed without sacrificing signal quality. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with new structures. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality.","abstract_html":"The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have been rapidly developed. Because of FPGAs’ high speed, high integration and field-programmable advantages, the devices are widely used in digital processing and are increasingly favored by hardware circuit design engineers. FPGAs also provide a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such high-speed switching, fine tunability and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate some ways to optimize the DDS structure to save hardware resources and increase chip speed without sacrificing signal quality. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with new structures. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality.","abstract_has_math":false,"creators":["Li, Zexian"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Schutt-Ainé, José E."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2019,"date_issued":"2019-02-07T20:44:24Z","date_published":"2019-02-07T20:44:24Z","updated_at":"2026-07-22T22:24:42Z","subjects":["DDS, FPGA, STA"],"languages":["en"],"rights":["Copyright 2018 Zexian Li"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/102841","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Schutt-Ainé, José E."]},{"key":"dc:creator","label":"Author","values":["Li, Zexian"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2019-02-07T20:44:24Z","2021-02-08T10:15:11Z","2018-12-13","2018-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["DDS, FPGA, STA"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2018 Zexian Li"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/102841"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have been rapidly developed. Because of FPGAs’ high speed, high integration and field-programmable advantages, the devices are widely used in digital processing and are increasingly favored by hardware circuit design engineers. FPGAs also provide a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such high-speed switching, fine tunability and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate some ways to optimize the DDS structure to save hardware resources and increase chip speed without sacrificing signal quality. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with new structures. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2020-12-01","The student, Zexian Li, accepted the attached license on 2018-12-13 at 15:46.","The student, Zexian Li, submitted this Thesis for approval on 2018-12-13 at 15:47.","This Thesis was approved for publication on 2018-12-13 at 16:05.","DSpace SAF Submission Ingestion Package generated from Vireo submission #13230 on 2019-02-07 at 14:22:53","Made available in DSpace on 2019-02-07T20:44:24Z (GMT). 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With the development of microelectronics technology, field-programmable gate array (FPGA) devices have been rapidly developed. Because of FPGAs’ high speed, high integration and field-programmable advantages, the devices are widely used in digital processing and are increasingly favored by hardware circuit design engineers. FPGAs also provide a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such high-speed switching, fine tunability and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate some ways to optimize the DDS structure to save hardware resources and increase chip speed without sacrificing signal quality. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with new structures. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2020-12-01","The student, Zexian Li, accepted the attached license on 2018-12-13 at 15:46.","The student, Zexian Li, submitted this Thesis for approval on 2018-12-13 at 15:47.","This Thesis was approved for publication on 2018-12-13 at 16:05.","DSpace SAF Submission Ingestion Package generated from Vireo submission #13230 on 2019-02-07 at 14:22:53","Made available in DSpace on 2019-02-07T20:44:24Z (GMT). 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