{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/101358"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/101358","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Architectural exploration of Si-IF many-die processors","abstract":"Embargo set by: Seth Robbins for item 107443 Lift date: 2020-09-04T20:50:11Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","abstract_html":"Embargo set by: Seth Robbins for item 107443 Lift date: 2020-09-04T20:50:11Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","abstract_has_math":false,"creators":["Petrisko, Daniel"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kumar, Rakesh"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2018,"date_issued":"2018-09-04T20:47:27Z","date_published":"2018-09-04T20:47:27Z","updated_at":"2026-07-22T22:24:38Z","subjects":["Computer Architecture","Design Space Exploration","Waferscale","GPU","Si-IF"],"languages":["en"],"rights":["Copyright 2018 Daniel Petrisko"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/101358","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kumar, Rakesh"]},{"key":"dc:creator","label":"Author","values":["Petrisko, Daniel"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2018-09-04T20:47:27Z","2018-04-25","2018-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Architecture","Design Space Exploration","Waferscale","GPU","Si-IF"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2018 Daniel Petrisko"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/101358"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Embargo set by: Seth Robbins for item 107443 Lift date: 2020-09-04T20:50:11Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Open Restriction set for Item 107443 on 2019-05-09T15:52:26Z with date null by fschaef2@illinois.edu.","Open Restriction set for Item 107443 on 2019-05-09T15:52:28Z with date null by fschaef2@illinois.edu.","Open","Monolithic, single-die processors dominate today’s computing landscape. High performance systems achieve massive throughput by connecting large numbers of discrete chips – CPUs, GPUs, FPGAs – through high latency, low bandwidth interconnects. However, such systems provide limited performance scaling due to high communication costs between the discrete chips. This thesis proposes an alternate path for performance scaling: integrating many dies onto a single chip using a novel assembly technology – Silicon Interconnect Fabric (Si-IF). Many-die processors have both a technical and an economic advantage over their monolithic counterparts. We demonstrate potential benefits of a many-die approach using two approaches: efficient workload coverage design space exploration using many dies and evaluating a many-die wafer-scale GPU design.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2020-05-01","The student, Daniel Petrisko, accepted the attached license on 2018-04-24 at 12:27.","The student, Daniel Petrisko, submitted this Thesis for approval on 2018-04-24 at 12:41.","This Thesis was approved for publication on 2018-04-25 at 08:30.","DSpace SAF Submission Ingestion Package generated from Vireo submission #12382 on 2018-08-31 at 17:30:09","Made available in DSpace on 2018-09-04T20:47:27Z (GMT). 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High performance systems achieve massive throughput by connecting large numbers of discrete chips – CPUs, GPUs, FPGAs – through high latency, low bandwidth interconnects. However, such systems provide limited performance scaling due to high communication costs between the discrete chips. This thesis proposes an alternate path for performance scaling: integrating many dies onto a single chip using a novel assembly technology – Silicon Interconnect Fabric (Si-IF). Many-die processors have both a technical and an economic advantage over their monolithic counterparts. We demonstrate potential benefits of a many-die approach using two approaches: efficient workload coverage design space exploration using many dies and evaluating a many-die wafer-scale GPU design.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2020-05-01","The student, Daniel Petrisko, accepted the attached license on 2018-04-24 at 12:27.","The student, Daniel Petrisko, submitted this Thesis for approval on 2018-04-24 at 12:41.","This Thesis was approved for publication on 2018-04-25 at 08:30.","DSpace SAF Submission Ingestion Package generated from Vireo submission #12382 on 2018-08-31 at 17:30:09","Made available in DSpace on 2018-09-04T20:47:27Z (GMT). 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