{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/101104"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/101104","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Resonant-type architectures for active power decoupling in grid-tied single-phase power electronics","abstract":"In single-phase power converters, twice-line frequency power decoupling circuits are used to buffer the instantaneous energy difference between the AC and DC sides of the converter. Active buffer implementations are used to reduce the volume and potentially improve the reliability of the converter by redistributing passive energy storage requirements with combinations of switches, capacitors, and inductors. This thesis applies resonant impedance behavior to the operation of a specific DC-side twice-line frequency buffer called a series-stacked buffer (SSB). Utilizing this equivalent impedance model, an appropriate voltage-control scheme is derived and experimentally validated. There is also additional consideration of energy performance metrics in the context of DC-side buffers. Furthermore, the SSB equivalent impedance model is extended, applied, and generalized to the full single-phase converter system. This analysis includes an integrated system control method which imposes phase-locking and consistent transient stability. Experimental verification of full system interconnectivity is validated with a 1.5 kW power factor correction (PFC) boost flying capacitor multilevel (FCML) converter.","abstract_html":"In single-phase power converters, twice-line frequency power decoupling circuits are used to buffer the instantaneous energy difference between the AC and DC sides of the converter. Active buffer implementations are used to reduce the volume and potentially improve the reliability of the converter by redistributing passive energy storage requirements with combinations of switches, capacitors, and inductors. This thesis applies resonant impedance behavior to the operation of a specific DC-side twice-line frequency buffer called a series-stacked buffer (SSB). Utilizing this equivalent impedance model, an appropriate voltage-control scheme is derived and experimentally validated. There is also additional consideration of energy performance metrics in the context of DC-side buffers. Furthermore, the SSB equivalent impedance model is extended, applied, and generalized to the full single-phase converter system. This analysis includes an integrated system control method which imposes phase-locking and consistent transient stability. Experimental verification of full system interconnectivity is validated with a 1.5 kW power factor correction (PFC) boost flying capacitor multilevel (FCML) converter.","abstract_has_math":false,"creators":["Brooks, Nathan C."],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Pilawa-Podgurski, Robert C.N."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2018,"date_issued":"2018-09-04T20:32:05Z","date_published":"2018-09-04T20:32:05Z","updated_at":"2026-07-22T22:24:38Z","subjects":["single-phase, power decoupling, active energy buffer, twice-line frequency, efficiency, resonant buffer, series-stacked buffer"],"languages":["en"],"rights":["Copyright 2018 Nathan C. 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There is also additional consideration of energy performance metrics in the context of DC-side buffers. Furthermore, the SSB equivalent impedance model is extended, applied, and generalized to the full single-phase converter system. This analysis includes an integrated system control method which imposes phase-locking and consistent transient stability. Experimental verification of full system interconnectivity is validated with a 1.5 kW power factor correction (PFC) boost flying capacitor multilevel (FCML) converter.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2018-08-31 without embargo terms","The student, Nathan Brooks, accepted the attached license on 2018-04-27 at 15:24.","The student, Nathan Brooks, submitted this Thesis for approval on 2018-04-27 at 15:51.","This Thesis was approved for publication on 2018-04-27 at 16:01.","DSpace SAF Submission Ingestion Package generated from Vireo submission #12546 on 2018-08-31 at 17:15:19","Made available in DSpace on 2018-09-04T20:32:05Z (GMT). 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Active buffer implementations are used to reduce the volume and potentially improve the reliability of the converter by redistributing passive energy storage requirements with combinations of switches, capacitors, and inductors. This thesis applies resonant impedance behavior to the operation of a specific DC-side twice-line frequency buffer called a series-stacked buffer (SSB). Utilizing this equivalent impedance model, an appropriate voltage-control scheme is derived and experimentally validated. There is also additional consideration of energy performance metrics in the context of DC-side buffers. Furthermore, the SSB equivalent impedance model is extended, applied, and generalized to the full single-phase converter system. This analysis includes an integrated system control method which imposes phase-locking and consistent transient stability. Experimental verification of full system interconnectivity is validated with a 1.5 kW power factor correction (PFC) boost flying capacitor multilevel (FCML) converter.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2018-08-31 without embargo terms","The student, Nathan Brooks, accepted the attached license on 2018-04-27 at 15:24.","The student, Nathan Brooks, submitted this Thesis for approval on 2018-04-27 at 15:51.","This Thesis was approved for publication on 2018-04-27 at 16:01.","DSpace SAF Submission Ingestion Package generated from Vireo submission #12546 on 2018-08-31 at 17:15:19","Made available in DSpace on 2018-09-04T20:32:05Z (GMT). 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