{"id":{"repo_id":"ttu","oai_identifier":"oai:ttu-ir.tdl.org:2346/20518"},"canonical_url":"https://search.dev.ndltd.org/etd/ttu/oai:ttu-ir.tdl.org:2346/20518","repository":{"repo_id":"ttu","name":"Texas Technology University","base_url":"https://ttu-ir.tdl.org/server/oai/request"},"display":{"title":"Algorithms for circuit layout compaction of building blocks","abstract":"Compaction is the CAD tool used to pack rough sketches or symbolic diagrams to produce error free IC layouts. With the ever increasing complexity of VLSI circuitry, the building block approach becomes very important for custom VLSI design. A graph-theoretic compaction algorithm is developed for the compaction of symbolically specified layouts of building block LSI's. The layout area is reduced by minimizing the pitch in each dimension separately. The algorithm is capable of handling mixed constraints; i.e., the constraints arising from design rule requirements (lower-bound type), and the User defined constraints (equality and upper-bound type).","abstract_html":"Compaction is the CAD tool used to pack rough sketches or symbolic diagrams to produce error free IC layouts. With the ever increasing complexity of VLSI circuitry, the building block approach becomes very important for custom VLSI design. A graph-theoretic compaction algorithm is developed for the compaction of symbolically specified layouts of building block LSI's. The layout area is reduced by minimizing the pitch in each dimension separately. The algorithm is capable of handling mixed constraints; i.e., the constraints arising from design rule requirements (lower-bound type), and the User defined constraints (equality and upper-bound type).","abstract_has_math":false,"creators":["Varadarajan, Ramachandran"],"institution":"Texas Tech University","degree_name":"M.S.","degree_level":"Masters","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":1985,"date_issued":"1985-12","date_published":"1985-12","updated_at":"2026-07-24T05:04:47Z","subjects":["Computer architecture","Integrated circuits","Computer-aided design","Algorithms"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2346/20518","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Varadarajan, Ramachandran"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.available","label":"Dc Date Available","values":["2011-02-18T23:45:54Z"]},{"key":"dc:date.issued","label":"Date","values":["1985-12"]},{"key":"dc:publisher","label":"Institution","values":["Texas Tech University"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Texas Tech University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer architecture","Integrated circuits","Computer-aided design","Algorithms"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/2346/20518"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Compaction is the CAD tool used to pack rough sketches or symbolic diagrams to produce error free IC layouts. With the ever increasing complexity of VLSI circuitry, the building block approach becomes very important for custom VLSI design. A graph-theoretic compaction algorithm is developed for the compaction of symbolically specified layouts of building block LSI's. The layout area is reduced by minimizing the pitch in each dimension separately. The algorithm is capable of handling mixed constraints; i.e., the constraints arising from design rule requirements (lower-bound type), and the User defined constraints (equality and upper-bound type)."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Algorithms for circuit layout compaction of building blocks"]}]}],"canonical_facts":{"dc:creator":["Varadarajan, Ramachandran"],"dc:date.available":["2011-02-18T23:45:54Z"],"dc:date.issued":["1985-12"],"dc:description.abstract":["Compaction is the CAD tool used to pack rough sketches or symbolic diagrams to produce error free IC layouts. With the ever increasing complexity of VLSI circuitry, the building block approach becomes very important for custom VLSI design. A graph-theoretic compaction algorithm is developed for the compaction of symbolically specified layouts of building block LSI's. The layout area is reduced by minimizing the pitch in each dimension separately. The algorithm is capable of handling mixed constraints; i.e., the constraints arising from design rule requirements (lower-bound type), and the User defined constraints (equality and upper-bound type)."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/2346/20518"],"dc:language.iso":["eng"],"dc:publisher":["Texas Tech University"],"dc:subject":["Computer architecture","Integrated circuits","Computer-aided design","Algorithms"],"dc:title":["Algorithms for circuit layout compaction of building blocks"],"dc:type":["Thesis"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Masters"],"thesis:degree_name":["M.S."],"thesis:institution_name":["Texas Tech University"]},"updated_at":"2026-07-24T05:04:47Z"}