{"id":{"repo_id":"toronto-retro","oai_identifier":"oai:utoronto.scholaris.ca:1807/90136"},"canonical_url":"https://search.dev.ndltd.org/etd/toronto-retro/oai:utoronto.scholaris.ca:1807/90136","repository":{"repo_id":"toronto-retro","name":"University of Toronto","base_url":"https://utoronto.scholaris.ca/server/oai/request"},"display":{"title":"A Variable Gain Direct Digital Readout System for Capacitive Inertial Sensors","abstract":"High fidelity interface circuits for capacitive accelerometers make use of feedback for signal detection but these feedback systems are limited by the sense capacitance and sensitivity of the accelerometers. This problem is addressed by a variable gain delta sigma based interface circuit that time multiplexes the accelerometer sense capacitance between the feedforward gain stage and feedback digital to analog (DAC) stage. Interfaced with a commercial accelerometer with sensitivity of 4.5 fF/g, the circuit achieves 40.6 dB SNDR in the x-direction and 42.5 dB SNDR in the y-direction due to limitations of the available testing equipment. With proper equipment, the system has the potential to achieve 53.0 and 54.9 dB SNDR in the x and y direction respectively while significantly reducing harmonics associated with the non-linear variable sense capacitors. Other interface circuits using the same sensor at comparable power would achieve linearity below 40 dB due to the limitation of the feedback structure.","abstract_html":"High fidelity interface circuits for capacitive accelerometers make use of feedback for signal detection but these feedback systems are limited by the sense capacitance and sensitivity of the accelerometers. This problem is addressed by a variable gain delta sigma based interface circuit that time multiplexes the accelerometer sense capacitance between the feedforward gain stage and feedback digital to analog (DAC) stage. Interfaced with a commercial accelerometer with sensitivity of 4.5 fF/g, the circuit achieves 40.6 dB SNDR in the x-direction and 42.5 dB SNDR in the y-direction due to limitations of the available testing equipment. With proper equipment, the system has the potential to achieve 53.0 and 54.9 dB SNDR in the x and y direction respectively while significantly reducing harmonics associated with the non-linear variable sense capacitors. Other interface circuits using the same sensor at comparable power would achieve linearity below 40 dB due to the limitation of the feedback structure.","abstract_has_math":false,"creators":["Amini, Saber"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":["Johns, David Andrew"],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017-11","date_published":"2017-11","updated_at":"2026-07-27T21:27:56Z","subjects":["accelerometers","charge balanced","flexible","interface circuits","ratiometric","readout circuits"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1807/90136","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Johns, David Andrew"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Amini, Saber"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2017-11"]},{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2018-08-08T17:00:13Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2018-08-08T17:00:13Z"]},{"key":"dc:date.issued","label":"Date","values":["2017-11"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["accelerometers","charge balanced","flexible","interface circuits","ratiometric","readout circuits"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1807/90136"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["High fidelity interface circuits for capacitive accelerometers make use of feedback for signal detection but these feedback systems are limited by the sense capacitance and sensitivity of the accelerometers. This problem is addressed by a variable gain delta sigma based interface circuit that time multiplexes the accelerometer sense capacitance between the feedforward gain stage and feedback digital to analog (DAC) stage. Interfaced with a commercial accelerometer with sensitivity of 4.5 fF/g, the circuit achieves 40.6 dB SNDR in the x-direction and 42.5 dB SNDR in the y-direction due to limitations of the available testing equipment. With proper equipment, the system has the potential to achieve 53.0 and 54.9 dB SNDR in the x and y direction respectively while significantly reducing harmonics associated with the non-linear variable sense capacitors. Other interface circuits using the same sensor at comparable power would achieve linearity below 40 dB due to the limitation of the feedback structure."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph.D."]},{"key":"dc:title","label":"Title","values":["A Variable Gain Direct Digital Readout System for Capacitive Inertial Sensors"]}]}],"canonical_facts":{"dc:contributor.advisor":["Johns, David Andrew"],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Amini, Saber"],"dc:date":["2017-11"],"dc:date.accessioned":["2018-08-08T17:00:13Z"],"dc:date.available":["2018-08-08T17:00:13Z"],"dc:date.issued":["2017-11"],"dc:description.abstract":["High fidelity interface circuits for capacitive accelerometers make use of feedback for signal detection but these feedback systems are limited by the sense capacitance and sensitivity of the accelerometers. This problem is addressed by a variable gain delta sigma based interface circuit that time multiplexes the accelerometer sense capacitance between the feedforward gain stage and feedback digital to analog (DAC) stage. Interfaced with a commercial accelerometer with sensitivity of 4.5 fF/g, the circuit achieves 40.6 dB SNDR in the x-direction and 42.5 dB SNDR in the y-direction due to limitations of the available testing equipment. With proper equipment, the system has the potential to achieve 53.0 and 54.9 dB SNDR in the x and y direction respectively while significantly reducing harmonics associated with the non-linear variable sense capacitors. Other interface circuits using the same sensor at comparable power would achieve linearity below 40 dB due to the limitation of the feedback structure."],"dc:description.degree":["Ph.D."],"dc:identifier.uri":["http://hdl.handle.net/1807/90136"],"dc:subject":["accelerometers","charge balanced","flexible","interface circuits","ratiometric","readout circuits"],"dc:title":["A Variable Gain Direct Digital Readout System for Capacitive Inertial Sensors"],"dc:type":["Thesis"]},"updated_at":"2026-07-27T21:27:56Z"}