Adaptive Blocker Cancellation For Wireless Receivers

This thesis targets cancellation of unwanted signals (blockers), one of the most difficult requirements for a wireless receiver. Current state-of-the-art analog filtering ADCs are analyzed and compared in detail. Recognizing that the analog circuitry requires accurate calibration and PVT correction, a digital filtering ADC in the baseband is proposed that has a digitally defined transfer function that is highly reconfigurable and insensitive to PVT variations. A blocker adaptation algorithm is also presented that tracks the blocker in real time and takes approximately 26ms to converge. The proposed architecture is demonstrated in a wireless receiver prototype implemented in 28nm CMOS technology. The measured programmable digital filter provides 34.9dB attenuation of TX leakage and variable attenuation of an additional blocker anywhere in the frequency range 17.5MHz–107.5MHz. The receiver front-end operates at 1.8GHz with a noise figure of 3.9dB, IIP3 of -5dBm, and consumes only 20.4–37.5mW, the lowest among state-of-the-art designs.

Department dc:contributor.department

Electrical and Computer Engineering

Year dc:date.issued

2018

Author dc:creator

• Wang, Qiwei

Advisors dc:contributor.advisor

• Chan Carusone, Anthony
• Liscdini, Antonio

Handle dc:identifier.uri

http://hdl.handle.net/1807/89780

OAI identifier oai:identifier

oai:utoronto.scholaris.ca:1807/89780