Fine-grained Adaptivity for Dynamic On-chip Networks

A key challenge of building chip multiprocessors (CMPs) is providing an efficient communication infrastructure for their increasing communication demands. Networks-on-Chip (NoCs) offer a scalable, high-bandwidth, low-latency solution to this problem, but unfortunately incur significant area and power overheads. Current NoCs are mostly agnostic to application requirements and hence are statically provisioned for worst-case traffic scenarios, leading to wasted energy and performance. Based on our observations that a static NoC design cannot optimally support the constantly changing communication requirements of modern, multi-threaded applications, this dissertation proposes fine-grained adaptivity for NoCs. Fine-grained adaptive NoCs provide the ability to adjust NoC resources to the dynamically changing communication requirements during runtime. Specifically, we introduce three novel, adaptive NoC designs that each target a particular area of fine-grained adaptivity. Firstly, we focus on dynamically changing bandwidth requirements and propose fine-grained bandwidth adaptivity. Existing NoCs only use 5% of channel resources on average to avoid performance penalties during phases of high utilization. Our architecture uses fine-grained bandwidth-adaptive bidirectional channels and exploits temporal and spatial variations in bandwidth requirements to improve channel utilization. Our second proposed design focuses on variations in communication locality for hierarchical NoCs. Previous hierarchical NoCs support communication locality only for a fixed cluster of nodes; however, providing a fixed hierarchy is too restrictive in terms of parallelism and data placement. Therefore, we propose a new, more flexible class of hierarchical NoCs: Elastic Hierarchical NoCs. Elastic Hierarchical NoCs dynamically adjust the number and size of clusters during runtime according to the system's communication demands. Our third proposed design targets the prediction of fine-grained variations in communication requirements for dynamic voltage and frequency scaling (DVFS). Efficient DVFS relies on accurate predictions of future network state. While previous approaches are reactive and based on network-centric metrics, we find that these metrics lead to suboptimal DVFS decisions. Instead, we propose to utilize highly predictable properties of cache-coherence communication to derive more specific and reliable NoC traffic predictions. These three innovative designs advance the state-of-the-art by allowing NoCs to adapt to spatially and temporally changing communication requirements during runtime; thereby significantly improving their performance and energy efficiency.

Department dc:contributor.department

Electrical and Computer Engineering

Year dc:date.issued

2016

Author dc:creator

• Hesse, Robert

Advisor dc:contributor.advisor

• Enright Jerger, Natalie

• chip multiprocessor
• computer architecture
• many-core
• Network-on-Chip
• NoC

Handle dc:identifier.uri

http://hdl.handle.net/1807/73014

OAI identifier oai:identifier

oai:utoronto.scholaris.ca:1807/73014