Applications of Machine Learning in the Design and Optimization of Analog Integrated Circuits and Systems

Analog integrated circuits (ICs) and systems are widely used in various applications such as data communication, biological sensing, and audio/video signal processing. The design of such circuits and systems has become tremendously complicated and challenging due to technological advancements and the need for faster, more energy-efficient, and accessible data processing power. Unlike their digital counterparts, analog circuit design often lacks automation and requires many design iterations to achieve the target specifications. With the recent development of artificial intelligence (AI), machine learning (ML) has become a focal research area in analog IC design. ML can play two fundamental roles when used in analog IC and system design. First, it can be used as a predictor, enabling prompt inference of output from input. Second, it can be used as an optimizer. Several ML applications will be discussed in this thesis. In the first practice, a T-coil-enhanced electrostatic discharge (ESD) circuit optimization scheme is presented, where a novel up-sampling convolutional neural network (CNN) is proposed to quickly predict the S-parameter of a T-coil from DC to 100 GHz from its layout geometric parameters, thereby bypassing the need for time-consuming electromagnetic simulations in the optimization phase. Our second application considers the optimization of a 64 Gbaud PAM-4 ADC-based optical receiver behavioural model, in which the previously proposed T-coil-enhanced ESD circuit optimization scheme is embedded. The third application uses reinforcement learning (RL) techniques to optimize critical analog IC blocks, such as low-dropout voltage regulators (LDOs) and latched comparators like StrongARM and double-tail architectures. These optimizations are demonstrated using open-source process development kits (PDKs) SKY130 and GF180MCU. Finally, inspired by an open-source analog circuit layout generation tool, a complete specification-to-layout design cycle is proposed.

Department dc:contributor.department

Electrical and Computer Engineering

Year dc:date.issued

2025

Author dc:creator

• Li, Zonghao

Advisor dc:contributor.advisor

• Carusone, Anthony C

• analog integrated circuit
• electronic design automation
• machine learning
• optimization
• reinforcement learning
• wireline communication

Statement dc:rights

• Attribution 4.0 International

Licence dc:rights.uri

• http://creativecommons.org/licenses/by/4.0/

Handle dc:identifier.uri

https://hdl.handle.net/1807/145122

OAI identifier oai:identifier

oai:utoronto.scholaris.ca:1807/145122