Power-Efficient Voltage-Mode RF Front-End Using Quantized Analog Signal Processing

In favour of saving precious real-estate and reducing overall cost for modern RF front-ends, SAW (Surface Acoustic Wave)-less RF receivers have become a popular topic recently. Unfortunately, removal of SAW filters requires the receiver to handle large blockers (e.g., above 0 dBm) without degrading the noise floor and in turn increases the overall power consumption of both the signal and local oscillator (LO) paths. My contributions to the state-of-the-art SAW-less receivers for my PhD addresses the abovementioned issues and can be summarized in the following major points: 1) for the first time, voltage-mode approach was made compliant to modern SAW-less receiver specs by the use of Quantized Analog (QA) signal processing, 2) for the first time, power scalability feature for the LO is introduced where LO power is scaled based on the operative scenario, leading to a significant power reduction compared to state-of-the-art (e.g., down to 1.6 mW for the LO), 3) an automated calibration platform was developed for the QA receiver where it significantly increased the linearity performance (e.g., up to 33 dB improvement for both third-order and second-order intermodulation products compared to non-calibrated), and 4) a novel multi-stage QA low-noise amplifier (LNA) was investigated with the introduction of tree architecture which dramatically reduces the power consumption and input capacitance when large input swing for the LNA is required.The first chapter reviews the state-of-the-art SAW-less receivers which identifies the core issue of excessive power consumption in these modern receivers and to appreciate the outlined solutions presented in this thesis. Chapter 2 presents the employed design strategies in the proposed receiver to address the excessive power. In chapter 3, the proposed SAW-less RF receiver design is presented as well as the manufactured test chip with its measurement results, with the results verifying points 1) and 2) above. Chapter 4 provides the automation calibration platform developed to increase overall linearity performance of the first QA test chip described in point 3) above. In chapter 5, the novel tree QA architecture is presented along with simulation results verifying point 4) above. The last chapter provides concluding remarks of the entire thesis.

Department dc:contributor.department

Electrical and Computer Engineering

Year dc:date.issued

2023

Author dc:creator

• Kim, Justin Yonghui

Advisor dc:contributor.advisor

• Liscidini, Antonio

• Digital calibration
• Power efficient
• Power scalable
• Quantized Analog
• RFIC
• SAW-less

Handle dc:identifier.uri

http://hdl.handle.net/1807/128225

OAI identifier oai:identifier

oai:utoronto.scholaris.ca:1807/128225