A Distortion Suppression Technique for a Digital Class D Audio Power Amplifier with Pulse Density Modulation

Researchers in industry and academia have been optimizing audio amplifier designs with novel architectures to keep up with growing demands for high sound quality and improved power efficiency. Low power audio amplifiers for mobile phones and MP3 players, and high power amplifiers for portable speakers require high power efficiency and superior audio quality. The compact design of portable electronics has also increased the need to reduce the amount of Electromagnetic Interference (EMI) generated. Switching audio Class D amplifiers can provide much better power efficiency than linear Class AB amplifiers due to a low voltage difference between the switching output node and the power supplies. Pulse Width Modulation (PWM) can provide over 100 dB THD at a switching rate well below 1 MHz, but can generate large EMI spikes at the switching frequency and harmonics. Many techniques have been developed to reduce this problem, such as spread spectrum switching and adaptive gate drive. Pulse Density Modulation (PDM) uses a noise shaping Delta Sigma Modulator (DSM), and generally requires a higher switching rate than PWM to obtain comparable THD performance. Techniques such as hysteresis can be used to reduce the rate to comparable levels. PDM also generates a more randomized switching pattern, which results in lower EMI than PWM. In this thesis, a novel distortion suppression technique suitable for digital class D audio power amplifiers using pulse density modulation (DSM) is presented. The distortion suppression circuit generates a digital measurement of the output stage error, and feeds it back to the DSM for noise shaping. Digitization of the error signal, and not the full scale output, in the feedback path requires a lower resolution ADC than previous solutions have required. It is shown the feedback scheme can tolerate long latency. The amplifier generates 100 dB SNR and 12 W power with an 8 Ohm load. Experimental verification via a printed circuit board (PCB) prototype shows 10 dB reduction in THD at -8 dB (relative to full scale input) and 28 dB attenuation of intermodulation distortion, with a feedback latency of 16 clock cycles for a DSM clock of 12.5 MHz.

Department dc:contributor.department

Electrical and Computer Engineering

Year dc:date.issued

2022

Author dc:creator

• McKenzie, Robert Neil

Advisor dc:contributor.advisor

• Ng, Wai Tung

Handle dc:identifier.uri

http://hdl.handle.net/1807/123454

OAI identifier oai:identifier

oai:utoronto.scholaris.ca:1807/123454