{"id":{"repo_id":"texas","oai_identifier":"oai:repositories.lib.utexas.edu:2152/ETD-UT-2012-08-6222"},"canonical_url":"https://search.dev.ndltd.org/etd/texas/oai:repositories.lib.utexas.edu:2152/ETD-UT-2012-08-6222","repository":{"repo_id":"texas","name":"University of Texas","base_url":"https://repositories.lib.utexas.edu/server/oai/request"},"display":{"title":"Stability analysis for SRAM cells with TSV induced stress in 3D ICs","abstract":"Three-dimensional integrated circuits (3D-IC) have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs while also helping to reduce wire delay and increase memory throughput. While this technology offers many potential advantages, it also produces large thermal mismatch stress in 3D-IC structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. TSV-induced stress effects on electron/hole mobility and device performance will be studied for the widely used 6-transistor (6T) SRAM cell. Simulation results in this study show that static noise margin (SNM), Read Margin (RM) and write margin (WM) tend to increase with decreasing electron mobility or increasing hole mobility. Considering TSV-induced stress, we propose that for practical layouts of TSV-based 3D-IC, p-type substrates should be placed further away from TSVs or closer to the smaller TSVs if multiple TSVs exist.","abstract_html":"Three-dimensional integrated circuits (3D-IC) have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs while also helping to reduce wire delay and increase memory throughput. While this technology offers many potential advantages, it also produces large thermal mismatch stress in 3D-IC structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. TSV-induced stress effects on electron/hole mobility and device performance will be studied for the widely used 6-transistor (6T) SRAM cell. Simulation results in this study show that static noise margin (SNM), Read Margin (RM) and write margin (WM) tend to increase with decreasing electron mobility or increasing hole mobility. Considering TSV-induced stress, we propose that for practical layouts of TSV-based 3D-IC, p-type substrates should be placed further away from TSVs or closer to the smaller TSVs if multiple TSVs exist.","abstract_has_math":false,"creators":["Zhang, Wen, 1990-"],"institution":"University of Texas at Austin","degree_name":"Master of Science in Engineering","degree_level":"Masters","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":[],"advisors":["Pan, David Z."],"committee_chairs":[],"committee_members":["Sun, Nan"],"year":2012,"date_issued":"2012-08","date_published":"2012-08","updated_at":"2026-07-24T05:00:56Z","subjects":["3D IC","Carrier mobility","Stability"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2152/ETD-UT-2012-08-6222","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Pan, David Z."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Sun, Nan"]},{"key":"dc:creator","label":"Author","values":["Zhang, Wen, 1990-"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2012-10-30T19:28:15Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2012-10-30T19:28:15Z"]},{"key":"dc:date.issued","label":"Date","values":["2012-08"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science in Engineering"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Texas at Austin"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["3D IC","Carrier mobility","Stability"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/2152/ETD-UT-2012-08-6222"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["text"]},{"key":"dc:description.abstract","label":"Abstract","values":["Three-dimensional integrated circuits (3D-IC) have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs while also helping to reduce wire delay and increase memory throughput. While this technology offers many potential advantages, it also produces large thermal mismatch stress in 3D-IC structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. TSV-induced stress effects on electron/hole mobility and device performance will be studied for the widely used 6-transistor (6T) SRAM cell. Simulation results in this study show that static noise margin (SNM), Read Margin (RM) and write margin (WM) tend to increase with decreasing electron mobility or increasing hole mobility. Considering TSV-induced stress, we propose that for practical layouts of TSV-based 3D-IC, p-type substrates should be placed further away from TSVs or closer to the smaller TSVs if multiple TSVs exist."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Stability analysis for SRAM cells with TSV induced stress in 3D ICs"]}]}],"canonical_facts":{"dc:contributor.advisor":["Pan, David Z."],"dc:contributor.committeemember":["Sun, Nan"],"dc:creator":["Zhang, Wen, 1990-"],"dc:date.accessioned":["2012-10-30T19:28:15Z"],"dc:date.available":["2012-10-30T19:28:15Z"],"dc:date.issued":["2012-08"],"dc:description":["text"],"dc:description.abstract":["Three-dimensional integrated circuits (3D-IC) have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs while also helping to reduce wire delay and increase memory throughput. While this technology offers many potential advantages, it also produces large thermal mismatch stress in 3D-IC structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. TSV-induced stress effects on electron/hole mobility and device performance will be studied for the widely used 6-transistor (6T) SRAM cell. Simulation results in this study show that static noise margin (SNM), Read Margin (RM) and write margin (WM) tend to increase with decreasing electron mobility or increasing hole mobility. Considering TSV-induced stress, we propose that for practical layouts of TSV-based 3D-IC, p-type substrates should be placed further away from TSVs or closer to the smaller TSVs if multiple TSVs exist."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/2152/ETD-UT-2012-08-6222"],"dc:language.iso":["eng"],"dc:subject":["3D IC","Carrier mobility","Stability"],"dc:title":["Stability analysis for SRAM cells with TSV induced stress in 3D ICs"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Masters"],"thesis:degree_name":["Master of Science in Engineering"],"thesis:institution_name":["University of Texas at Austin"]},"updated_at":"2026-07-24T05:00:56Z"}