{"id":{"repo_id":"texas","oai_identifier":"oai:repositories.lib.utexas.edu:2152/119321"},"canonical_url":"https://search.dev.ndltd.org/etd/texas/oai:repositories.lib.utexas.edu:2152/119321","repository":{"repo_id":"texas","name":"University of Texas","base_url":"https://repositories.lib.utexas.edu/server/oai/request"},"display":{"title":"Machine learning for analog/mixed-signal IC design : scaling from circuits to systems","abstract":"Analog and mixed-signal integrated circuits are widely used in many emerging applications, and the increasing demand calls for a shorter design cycle and time-to-market. Traditionally the design process is dominated by manual efforts and is very time-consuming, which involves design experts iterating between the circuit sizing and layout implementation steps. Despite attempts to automate the design process for analog circuits, prior works fail to scale from design automation of simple component level circuits to systems of larger size. Furthermore, few works have considered post-layout parasitic effects during circuit sizing, limiting the practical application in designing real chips targeting tape-out fabrication. This dissertation will explore methods to apply machine learning to analog and mixed signal circuit design automation in terms of practicality and scalability. Specifically, this dissertation will study and explore: Graph spectral and machine learning methods to automatically assign layout symmetry constraints from unannotated netlists of large circuit systems such as analog to digital converters (ADCs); Machine learning methods and models (such as convolutional neural networks and graph neural networks) to quantify analog layout quality and layout parasitic estimation without invoking parasitic extraction and circuit simulations; Efficient circuit sizing with Bayesian Optimization and in-the-loop layout generation that guarantees post layout performance, allowing design automation techniques to scale to the system-level design of an ADC. Finally, this work will be backed up by both circuit simulation results and real chip tape-out measurements to demonstrate the effectiveness of applying machine learning to automatically design analog circuits, which scales to analog system designs such as ADCs","abstract_html":"Analog and mixed-signal integrated circuits are widely used in many emerging applications, and the increasing demand calls for a shorter design cycle and time-to-market. Traditionally the design process is dominated by manual efforts and is very time-consuming, which involves design experts iterating between the circuit sizing and layout implementation steps. Despite attempts to automate the design process for analog circuits, prior works fail to scale from design automation of simple component level circuits to systems of larger size. Furthermore, few works have considered post-layout parasitic effects during circuit sizing, limiting the practical application in designing real chips targeting tape-out fabrication. This dissertation will explore methods to apply machine learning to analog and mixed signal circuit design automation in terms of practicality and scalability. Specifically, this dissertation will study and explore: Graph spectral and machine learning methods to automatically assign layout symmetry constraints from unannotated netlists of large circuit systems such as analog to digital converters (ADCs); Machine learning methods and models (such as convolutional neural networks and graph neural networks) to quantify analog layout quality and layout parasitic estimation without invoking parasitic extraction and circuit simulations; Efficient circuit sizing with Bayesian Optimization and in-the-loop layout generation that guarantees post layout performance, allowing design automation techniques to scale to the system-level design of an ADC. Finally, this work will be backed up by both circuit simulation results and real chip tape-out measurements to demonstrate the effectiveness of applying machine learning to automatically design analog circuits, which scales to analog system designs such as ADCs","abstract_has_math":false,"creators":["Liu, Mingjie"],"institution":"The University of Texas at Austin","degree_name":"Doctor of Philosophy","degree_level":"Doctoral","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":[],"advisors":["Pan, David Z."],"committee_chairs":[],"committee_members":["Sun, Nan","Kulkarni, Jaydeep P","Jia, Yaoyao","Ren, Haoxing"],"year":2022,"date_issued":"2022-11-27","date_published":"2022-11-27","updated_at":"2026-07-24T05:01:10Z","subjects":["Machine learning","Analog and mixed-signal circuits","Design automation"],"languages":["en"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://dx.doi.org/10.26153/tsw/46199"],"render_values":[{"text":"http://dx.doi.org/10.26153/tsw/46199","href":"http://dx.doi.org/10.26153/tsw/46199","code":true}]}]},"links":{"outbound_url":"https://hdl.handle.net/2152/119321","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Pan, David Z."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Sun, Nan","Kulkarni, Jaydeep P","Jia, Yaoyao","Ren, Haoxing"]},{"key":"dc:creator","label":"Author","values":["Liu, Mingjie"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2023-06-21T01:30:19Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2023-06-21T01:30:19Z"]},{"key":"dc:date.issued","label":"Date","values":["2022-11-27"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Doctoral"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["The University of Texas at Austin"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Machine learning","Analog and mixed-signal circuits","Design automation"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/2152/119321","http://dx.doi.org/10.26153/tsw/46199"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Analog and mixed-signal integrated circuits are widely used in many emerging applications, and the increasing demand calls for a shorter design cycle and time-to-market. Traditionally the design process is dominated by manual efforts and is very time-consuming, which involves design experts iterating between the circuit sizing and layout implementation steps. Despite attempts to automate the design process for analog circuits, prior works fail to scale from design automation of simple component level circuits to systems of larger size. Furthermore, few works have considered post-layout parasitic effects during circuit sizing, limiting the practical application in designing real chips targeting tape-out fabrication. This dissertation will explore methods to apply machine learning to analog and mixed signal circuit design automation in terms of practicality and scalability. Specifically, this dissertation will study and explore: Graph spectral and machine learning methods to automatically assign layout symmetry constraints from unannotated netlists of large circuit systems such as analog to digital converters (ADCs); Machine learning methods and models (such as convolutional neural networks and graph neural networks) to quantify analog layout quality and layout parasitic estimation without invoking parasitic extraction and circuit simulations; Efficient circuit sizing with Bayesian Optimization and in-the-loop layout generation that guarantees post layout performance, allowing design automation techniques to scale to the system-level design of an ADC. Finally, this work will be backed up by both circuit simulation results and real chip tape-out measurements to demonstrate the effectiveness of applying machine learning to automatically design analog circuits, which scales to analog system designs such as ADCs"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Machine learning for analog/mixed-signal IC design : scaling from circuits to systems"]}]}],"canonical_facts":{"dc:contributor.advisor":["Pan, David Z."],"dc:contributor.committeemember":["Sun, Nan","Kulkarni, Jaydeep P","Jia, Yaoyao","Ren, Haoxing"],"dc:creator":["Liu, Mingjie"],"dc:date.accessioned":["2023-06-21T01:30:19Z"],"dc:date.available":["2023-06-21T01:30:19Z"],"dc:date.issued":["2022-11-27"],"dc:description.abstract":["Analog and mixed-signal integrated circuits are widely used in many emerging applications, and the increasing demand calls for a shorter design cycle and time-to-market. Traditionally the design process is dominated by manual efforts and is very time-consuming, which involves design experts iterating between the circuit sizing and layout implementation steps. Despite attempts to automate the design process for analog circuits, prior works fail to scale from design automation of simple component level circuits to systems of larger size. Furthermore, few works have considered post-layout parasitic effects during circuit sizing, limiting the practical application in designing real chips targeting tape-out fabrication. This dissertation will explore methods to apply machine learning to analog and mixed signal circuit design automation in terms of practicality and scalability. Specifically, this dissertation will study and explore: Graph spectral and machine learning methods to automatically assign layout symmetry constraints from unannotated netlists of large circuit systems such as analog to digital converters (ADCs); Machine learning methods and models (such as convolutional neural networks and graph neural networks) to quantify analog layout quality and layout parasitic estimation without invoking parasitic extraction and circuit simulations; Efficient circuit sizing with Bayesian Optimization and in-the-loop layout generation that guarantees post layout performance, allowing design automation techniques to scale to the system-level design of an ADC. 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