Design methodologies for variation-aware integrated circuits

The scaling of VLSI technology has spurred a rapid growth in the semiconductor industry. With the CMOS device dimension scaling to and beyond 90nm technology, it is possible to achieve higher performance and to pack more complex functionalities on a single chip. However, the scaling trend has introduced drastic variation of process and design parameters, leading to severe variability of chip performance in nanometer regime. Also, the manufacturing community projects CMOS will scale for three to four more generations. Since the uncertainties due to variations are expected to increase in each generation, it will significantly impact the performance of design and consequently the yield. Another challenging issue in the nanometer IC design is the high power consumption due to the greater packing density, higher frequency of operation and excessive leakage power. Moreover, the circuits are usually over-designed to compensate for uncertainties due to variations. The over-designed circuits not only make timing closure difficult but also cause excessive power consumption. For portable electronics, excessive power consumption may reduce battery life; for non-portable systems it may impose great difficulties in cooling and packaging. The objective of my research has been to develop design methodologies to address variations and power dissipation for reliable circuit operation. The proposed work has been divided into three parts: the first part addresses the issues related with power/ground noise induced by clock distribution network and proposes techniques to reduce power/ground noise considering the effects of process variations. The second part proposes an elastic pipeline scheme for random circuits with feedback loops. The proposed scheme provides a low-power solution that has the same variation tolerance as the conventional approaches. The third section deals with discrete buffer and wire sizing for link-based non-tree clock network, which is an energy efficient structure for skew tolerance to variations. For the power/ground noise problem, our approach could reduce the peak current and the delay variations by 50% and 51% respectively. Compared to conventional approach, the elastic timing scheme reduces power dissipation by 20% ? 27%. The sizing method achieves clock skew reduction of 45% with a small increase in power dissipation.

Author dc:creator

• Samanta, Rupak

Contributors dc:contributor

• Hu, Jiang

• Clock
• Buffer
• Variation
• Power
• Noise
• Elastic
• Sizing

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/1969.1/ETD-TAMU-3119

OAI record oai:identifier

https://tdl-ir.tdl.org/server/oai/request?verb=GetRecord&metadataPrefix=dim&identifier=oai%3Atdl-ir.tdl.org%3A1969.1%2FETD-TAMU-3119