Transistor-Level Programmable Fabric

We introduce a CMOS computational fabric consisting of carefully arranged regular rows and columns of transistors which can be individually configured and appropriately interconnected in order to implement a target digital circuit. This TRAnsistor-level Programmable (TRAP) fabric allows simultaneous storage of four independent configurations, along with the ability to dynamically switch between them in a small fraction of a clock cycle. We term this board-level virtualization in that each configuration, in effect, implements an independent chip. TRAP also supports chip-level virtualization in which a single IC design is partitioned over a set of configurations and the computation cycles from one configuration to the next in the set. This allows a design that requires more computational logic than physically available on the TRAP chip to be nonetheless executable. TRAP also features rapid partial or full modification of any one of the stored configurations in a time proportional to the number of modified configuration bits through the use of hierarchically arranged, high throughput, pipelined memory buffers. TRAP supports libraries of cells of the same height and variable width, just as in a typical standard cell circuit. We developed a complete Computer-aided Design (CAD) tool flow for programming TRAP chips. A prototype 3mm X 3mm TRAP chip was fabricated using the Global Foundries 55nm process. We show that TRAP has substantially better area efficiency compared to a leading industrial FPGA and would, therefore, be ideal for embedded FPGA (eFPGA) applications.

Author dc:creator

• Tian, Jingxiang

Contributors dc:contributor

• Sechen, Carl
• Makris, Yiorgos

• Field programmable gate arrays
• Integrated circuits
• Information networks

Statement dc:rights

• ©2019 Jingxiang Tian. All Rights Reserved.

Language dc:language

en

Handle dc:identifier.uri

https://hdl.handle.net/10735.1/7364

OAI identifier oai:identifier

oai:tdl-ir.tdl.org:10735.1/7364