On the realisation of sequential fast fourier transform for orthogonal frequency division multiplexing based on field programmable gate array

In the last 25 years Digital Signal Processing (DSP) has become one of the key components in the development of mobile and wireless technologies. One of the core DSP algorithms widely used in many applications is the Fourier Transform, in both the standard Discrete Fourier Transform (DFT) and the Fast Fourier Transform (FFT) implementation. The DFT and FFT are widely used for many applications such as spectral analysis, but in modern mobile and wireless communications standards, their particular significance is in the context of the signalling strategy of Orthogonal Frequency Division Multiplexing (OFDM), where the FFT and Inverse FFT (IFFT) are deployed at the transmit and receive sides of both uplink and downlink. Over the last few years the physical layer of many 4th generation wireless standards, such as IEEE 802.20, IEEE 802.16, and 3GPP2, Ultra Mobile Broadband (UMB), as well as 3G Long Term Evaluation (LTE), all rely heavily on using OFDM multicarrier modulation. OFDM is now favoured in many physical layers for mobile and wireless radio systems, given that it has good properties for mitigating multipath propagation and operating in fading channels. In the implementation of OFDM, FFTs and IFFTs are required at various lengths, word lengths, speeds of operation, and on a variety of platforms such as DSP processors, Application Specific Integrated Circuits (ASICs) and - in basestations, mostly likely - on Field Programmable Gate Arrays (FPGAs). Therefore in this thesis we have focused on methods of efficient implementation of the FFT and IFFT on FPGAs, taking very clear note of issues such as resource costs, speeds, word length, and programmability. In this thesis, two FFT architectures have been introduced, the first based on the classic butterfly computation and the use of look-up tables to store FFT trigonometric constants, and the second based on using a COordinate Rotation Digital Computer (CORDIC) method to generate the trigonometric constant values. In this work, the FFT Radix-2 Decimation in Frequency (DIF) algorithm has been chosen and efficiently implemented on a Xilinx FPGA in a programmable form to suit a variety of PHY layer standards requirements. The design implements a pipelined sequential architecture to reduce the resource area and maintain high throughput. A key contribution is the introduction of an optimized butterfly processor that uses only two multipliers for the twiddle factor multiply, rather than the more conventional four as found in the designs available from FPGA vendors and IP repositories. The direct implementation of the butterfly requires four multipliers (to perform a complex data multiplication) and four corresponding block RAMs to store the input and output data. The proposed architecture utilises the 2 multipliers technique to reduce the resource cost, albeit it a cost of maximum throughput. For the CORDIC based design, no hardware multipliers are required since the CORDIC can directly implement the twiddle factor multiply. For both architectures to increase the speed of the FFT sequential architecture, a dual clock method has been used. To verify and generate demonstrable designs, the architectures have been simulated, synthesized and implemented on a Virtex 5/Xilinx FPGA.

Name dc:type.qualificationname

phd

Level dc:type.qualificationlevel

doctoral-pg

Grantor dc:publisher.institution

University of Strathclyde

Year dc:date.issued

2012

Author dc:creator

• Awad, Yousif

DOI

10.48730/ar0q-kz97

Identifier

T13318

OAI identifier oai:identifier

oai:strathclyde:02870v87z