ARCHITECTURE-AWARE HARD-REAL-TIME SCHEDULING ON MULTI-CORE ARCHITECTURES

The increasing dependency of man on machines have led to increase computational load on systems. The increasing computational load can be handled to some extent by scaling up processor frequencies. However, this approach has hit a frequency and power wall and the increasing awareness towards green computing discourages this solution. This leads us to use multi-core architectures. Due to the same reason, real-time systems are also migrating from single-core towards multi-core systems. While multi-core systems provide scalable high computational power, they also expose real-time systems to several challenges. Most of these challenges hamper the key property of real-time systems, i.e., predictability. In this work, we address some challenges imposed by multi-core architectures on real-time systems. We propose and evaluate several scheduling algorithms and demonstrate improved predictability and performance over existing methods. A unifying them in all our algorithms is that we explicitly consider the effects of architectural factors on the scheduling and schedulablity of real-time programs. As a case study, we use Tilera's TilePro64 platform as an example multi-core platform and implement some of our algorithms on this platform. Through this case study, we derive several useful conclusions regarding performance, predictability and practical overheads on a multi-core architecture.

Name thesis:degree_name

Doctor of Philosophy

Level thesis:degree_level

Campus Only Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Year

2014

Author dc:creator

• Shekhar, Mayank

Contributors dc:contributor

• Kagaris, Dimitrios

• Embedded Systems
• Hard Real-Time Systems
• Real-Time Systems
• Safety Critical
• Scheduling

Repository record dc:identifier

https://opensiuc.lib.siu.edu/dissertations/971

OAI identifier oai:identifier

oai:opensiuc.lib.siu.edu:dissertations-1975