{"id":{"repo_id":"siu-theses","oai_identifier":"oai:opensiuc.lib.siu.edu:dissertations-1291"},"canonical_url":"https://search.dev.ndltd.org/etd/siu-theses/oai:opensiuc.lib.siu.edu:dissertations-1291","repository":{"repo_id":"siu-theses","name":"Southern Illinois University","base_url":"https://opensiuc.lib.siu.edu/do/oai/"},"display":{"title":"SCALABLE TEST GENERATION FOR PATH DELAY FAULTS","abstract":"Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques to improve test generation for path delay faults. The first technique presented in this dissertation avoids testing unnecessary paths by using arithmetic operations. This second technique shows how to compact many faults into a single test application, thus saving valuable test application time. The third technique demonstrates how to generate tests under modern day scan architectures. Experimental results demonstrate the effectiveness of the proposed techniques.","abstract_html":"Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques to improve test generation for path delay faults. The first technique presented in this dissertation avoids testing unnecessary paths by using arithmetic operations. This second technique shows how to compact many faults into a single test application, thus saving valuable test application time. The third technique demonstrates how to generate tests under modern day scan architectures. Experimental results demonstrate the effectiveness of the proposed techniques.","abstract_has_math":false,"creators":["Flanigan, Edward"],"institution":null,"degree_name":"Doctor of Philosophy","degree_level":"Campus Only Dissertation","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Tragoudas, Spyros"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2009,"date_issued":"2009-01-01T08:00:00Z","date_published":"2009-01-01T08:00:00Z","updated_at":"2026-07-24T04:33:39Z","subjects":["PDF","Test","VLSI"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://opensiuc.lib.siu.edu/dissertations/291","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Tragoudas, Spyros"]},{"key":"dc:creator","label":"Author","values":["Flanigan, Edward"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Campus Only Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["PDF","Test","VLSI"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://opensiuc.lib.siu.edu/dissertations/291"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques to improve test generation for path delay faults. The first technique presented in this dissertation avoids testing unnecessary paths by using arithmetic operations. This second technique shows how to compact many faults into a single test application, thus saving valuable test application time. The third technique demonstrates how to generate tests under modern day scan architectures. Experimental results demonstrate the effectiveness of the proposed techniques."]},{"key":"dc:title","label":"Title","values":["SCALABLE TEST GENERATION FOR PATH DELAY FAULTS"]}]}],"canonical_facts":{"dc:contributor":["Tragoudas, Spyros"],"dc:creator":["Flanigan, Edward"],"dc:description.abstract":["Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques to improve test generation for path delay faults. The first technique presented in this dissertation avoids testing unnecessary paths by using arithmetic operations. This second technique shows how to compact many faults into a single test application, thus saving valuable test application time. The third technique demonstrates how to generate tests under modern day scan architectures. Experimental results demonstrate the effectiveness of the proposed techniques."],"dc:identifier":["https://opensiuc.lib.siu.edu/dissertations/291"],"dc:subject":["PDF","Test","VLSI"],"dc:title":["SCALABLE TEST GENERATION FOR PATH DELAY FAULTS"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Campus Only Dissertation"],"thesis:degree_name":["Doctor of Philosophy"]},"updated_at":"2026-07-24T04:33:39Z"}