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Rochester Institute of Technology
IEEE Compliant Double-Precision FPU and 64-bit ALU with Variable Latency Integer Divider
Degree
thesis:*- Name thesis:degree_name
- Computer Engineering (MS)
- Level thesis:degree_level
- Thesis
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Williams, Ryan D
- Contributors dc:contributor
-
- Kenneth W. Hsu
Identifiers
dc:identifier.*- Repository record dc:identifier
- https://repository.rit.edu/theses/7869
- OAI identifier oai:identifier
- oai:repository.rit.edu:theses-8874