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Rochester Institute of Technology

Subthreshold and gate leakage current analysis and reduction in VLSI circuits

dc:creator Chinta, Vinay

thesis:degree_name Computer Engineering (MS)

Degree

thesis:*

Name thesis:degree_name: Computer Engineering (MS)
Level thesis:degree_level: Thesis

Author and committee

dc:creator, dc:contributor.*

Author dc:creator: Chinta, Vinay
Contributors dc:contributor: Dhireesha Kudithipudi

Identifiers

dc:identifier.*

Repository record dc:identifier: https://repository.rit.edu/theses/7771
OAI identifier oai:identifier: oai:repository.rit.edu:theses-8776

Chain of custody

source

Harvested from: Rochester Institute of Technology
Base URL: repository.rit.edu/do/oai/
Last updated: 2026-07-27
Source record: OAI-PMH GetRecord

related terms

rit
Thesis

citation

Chinta, Vinay. Subthreshold and gate leakage current analysis and reduction in VLSI circuits. Thesis thesis, https://repository.rit.edu/theses/7771

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