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Rochester Institute of Technology

Computer Aided Design of the Pipelined Interconnect Free Logic

dc:creator Avachat, Vaibhav

thesis:degree_name Electrical Engineering (MS)

Degree

thesis:*

Name thesis:degree_name: Electrical Engineering (MS)
Level thesis:degree_level: Thesis

Author and committee

dc:creator, dc:contributor.*

Author dc:creator: Avachat, Vaibhav
Contributors dc:contributor: Dorin Patru

Identifiers

dc:identifier.*

Repository record dc:identifier: https://repository.rit.edu/theses/7706
OAI identifier oai:identifier: oai:repository.rit.edu:theses-8711

Chain of custody

source

Harvested from: Rochester Institute of Technology
Base URL: repository.rit.edu/do/oai/
Last updated: 2026-07-27
Source record: OAI-PMH GetRecord

related terms

rit
Thesis

citation

Avachat, Vaibhav. Computer Aided Design of the Pipelined Interconnect Free Logic. Thesis thesis, https://repository.rit.edu/theses/7706

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