Advanced MIMO-CDMA receiver for interference suppression: Algorithms, system-on-chip architectures and design methodology

MIMO (Multiple Input Multiple Output) technology is proposed in CDMA systems for much higher rate packet services. The receiver architecture is essential for the mobile devices to support high speed multimedia service. The design challenges come from both detection algorithms and hardware architectures. Much more complicated algorithms are required to suppress various interferences. However, the current hardware design architecture and methodology is falling far behind the requirements of small size, low cost and power consumption. System-On-Chip (SoC) architectures are a major revolution taking place in the design of integrated circuits due to many advantages in the power consumption and compact size. The VLSI-oriented complexity reduction of the numerical algorithms plays an essential role to design efficient real-time architectures. Thus, the thesis contributes to three major aspects: to propose high performance algorithms with realistic complexity in different channel conditions; to propose real-time SoC architectures with area/speed/power efficiency; and to propose an efficient design methodology for modelling, partitioning/binding, verification and synthesis of the wireless systems. Specifically, to cut the design cycle and enable extensive architecture tradeoff study, an integrated wireless development methodology by High-Level-Synthesis for joint algorithm and architecture optimization is proposed. To address the performance/complexity tradeoff, we propose two LMMSE equalizer algorithms and SoC architectures for different channel conditions. Both an FFT circulant MIMO equalizer and a frequency domain iterative equalizer are proposed to avoid Direct-Matrix-Inverse for the well-conditioned channel as well as long channels working in bad conditions respectively. We then propose a displacement Kalman equalizer with VLSI-oriented architectural optimization for better performance in fast fading environments. For systems with the multi-users' signaling, we propose an adaptive Parallel-Residue-Compensation architecture with stage and user specific weights by viewing the multiple transmitter antennas as virtual users to cancel the interferences explicitly. The increased accuracy in interference cancellation leads to significant performance gain over both the complete and partial PIC. The complexity is reduced by using the commonality to avoid the direct interference cancellation. Finally, dynamic power management schemes are proposed to reduce the power consumption in the VLSI architectures using the inherent features of the interference suppression algorithms.

Name thesis:degree_name

Doctor of Philosophy

Level thesis:degree_level

Doctoral

Discipline thesis:degree_discipline

Engineering

Grantor

Rice University

Year dc:date.issued

2005

Author dc:creator

• Guo, Yuanbin

Advisor dc:contributor.advisor

• Cavallaro, Joseph R.

• Electronics
• Electrical engineering
• Computer science

Statement dc:rights

• Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.

Language dc:language.iso

eng

Handle dc:identifier.uri

https://hdl.handle.net/1911/18845

OAI identifier oai:identifier

oai:repository.rice.edu:1911/18845