Architectural, numerical and implementation issues in the VLSI design of an integrated CORDIC-SVD processor

This thesis describes the design of a systolic array for computing the Singular Value Decomposition (SVD) based on the Brent, Luk, Van Loan array. The use of COordinate Rotation DIgital Computer (CORDIC) arithmetic results in an efficient VLSI implementation of the processor that forms the basic unit of the array. A six-chip custom VLSI chip set for the processor was initially designed, fabricated in a 2.0μ CMOS n-well process, and tested. The CORDIC Array Process Element (CAPE), a single chip implementation, incorporates several enhancements based on a detailed error analysis of fixed-point CORDIC. The analysis indicates a need to normalize input values for inverse tangent computations. This scheme was implemented using a novel method that has $O(n\sp{1.5})$ hardware complexity. Use of previous techniques to implement such a normalization would require $O(n\sp2)$ hardware. Enhanced architectures, which reduce idle time in the array either through pipelining or by improving on a broadcast technique, are also presented.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

Masters

Discipline thesis:degree_discipline

Engineering

Grantor

Rice University

Year dc:date.issued

1991

Author dc:creator

• Kota, Kishore

Advisor dc:contributor.advisor

• Cavallaro, Joseph R.

• Electronics
• Electrical engineering

Statement dc:rights

• Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.

Language dc:language.iso

eng

Handle dc:identifier.uri

https://hdl.handle.net/1911/13529

OAI identifier oai:identifier

oai:repository.rice.edu:1911/13529